 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| S25FL127S 128-mbit (16 mbyte) 3.0 v spi flash memory cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-98282 rev. *i revised june 08, 2017 features ? cmos 3.0 volt core ? density ? 128 mbits (16 mbytes) ? serial peripheral interf ace (spi) with multi-i/o ? spi clock polarity and phase modes 0 and 3 ? extended addressing: 24- or 32-bit address options ? serial command set and f ootprint compatible with s25fl-a, s25fl-k, and s25fl-p spi families ? multi i/o command set and footprint compatible with s25fl-p spi family ? read commands ? normal, fast, dual, quad ? autoboot - power up or reset and execute a normal or quad read command automat ically at a preselected address ? common flash interface (cfi) data for configuration information. ? programming (0.8 mbytes/s) ? 256- or 512-byte page programming buffer options ? quad-input page programming (qpp) for slow clock systems ? automatic ecc -internal ha rdware error correction code generation with single bit error correction ? erase (0.5 mbytes/s) ? hybrid sector size option - ph ysical set of sixteen 4-kbyte sectors at top or bottom of address space with all remaining sectors of 64 kbytes ? uniform sector option - always erase 256-kbyte blocks for software compatibility with higher density and future devices. ? cycling endurance ? 100,000 program-erase cycles per sector, minimum ? data retention ? 20 year data retention, minimum ? security features ? one time program (otp) array of 1024 bytes ? block protection: ? status register bits to control protection against program or erase of a contiguous range of sectors. ? hardware and software control options ? advanced sector protection (asp) ? individual sector protection controlled by boot code or password ? cypress ? 65 nm mirrorbit technology with eclipse ? architecture ? supply voltage: 2.7v to 3.6v ? temperature range: ? industrial (-40c to +85c) ? industrial plus (-40c to +105c) ? automotive aec-q100 grade 3 (-40c to +85c) ? automotive aec-q100 grade 2 (-40c to +105c) ? packages (all pb-free) ? 8-lead soic (208 mil) ? 16-lead soic (300 mil) ? 8-contact wson 6 x 5 mm ? bga-24 6 x 8 mm ? 5 x 5 ball (fab024) and 4 x 6 ball (fac024) footprint options ? known good die and known tested die
document number: 001-98282 rev. *i page 3 of 142 S25FL127S performance summary maximum read rates command clock rate (mhz) mbytes/s read 50 6.25 fast read 108 13.5 dual read 108 27 quad read 108 54 typical program and erase rates operation kbytes/s page programming (256-byte page buffer) 650 page programming (512-byte page buffer) 800 4-kbyte physical sector erase (hybrid sector option) 30 64-kbyte physical sector erase (hybrid sector option) 500 256-kbyte logical sector erase (uniform sector option) 500 current consumption operation current (ma) serial read 50 mhz 16 (max) serial read 108 mhz 24 (max) quad read 108 mhz 47 (max) program 50 (max) erase 50 (max) standby 0.07 (typ) document number: 001-98282 rev. *i page 3 of 142 S25FL127S contents performance summary ........................................................ 3 1. overview ....................................................................... 4 1.1 general description ....................................................... 4 1.2 migration notes.............................................................. 5 1.3 glossary......................................................................... 7 1.4 other resources............................................................ 8 2. signal descriptions ..................................................... 9 2.1 input/output summary................................................... 9 2.2 address and data configuration.................................. 10 2.3 hardware reset (r eset#)....... .............. .............. ....... 10 2.4 serial clock (sck) ....................................................... 10 2.5 chip select (cs#) ........................................................ 10 2.6 serial input (si) / io0 ................................................... 11 2.7 serial output (so) / io1............................................... 11 2.8 write protect (wp#) / io2 ............................................ 11 2.9 hold (hold#) / io3 / reset# .................................... 11 2.10 voltage supply (v cc )................................................... 12 2.11 supply and signal ground (v ss ) ................................. 12 2.12 not connected (nc) .................................................... 12 2.13 reserved for future use (rfu )................................... 12 2.14 do not use (dnu) ................. .............. .............. .......... 13 2.15 block diagrams............................................................ 13 3. signal protocols ......................................................... 15 3.1 spi clock modes ......................................................... 15 3.2 command protocol ...................................................... 15 3.3 interface states............................................................ 19 3.4 configuration register effects on the interface ........... 24 3.5 data protection ............................................................ 24 4. electrical specifications ............................................ 25 4.1 absolute maximum ratings ...... ................................... 25 4.2 operating ranges........................................................ 25 4.3 power-up and power-down ..... ................................... 26 4.4 dc characteristics ....................................................... 28 5. timing specifications ................................................ 29 5.1 key to switching waveforms . ...................................... 29 5.2 ac test conditions ...................................................... 30 5.3 reset............................................................................ 31 5.4 ac characteristics ....................................................... 34 6. physical interface ...................................................... 37 6.1 soic 8-lead package ................................................. 37 6.2 soic 16-lead package ............................................... 39 6.3 wson 6 x 5 package .................................................. 41 6.4 fab024 24-ball bga package .................................... 43 6.5 fac024 24-ball bga package .................................... 45 7. address space maps ................................................. 47 7.1 overview....................................................................... 47 7.2 flash memory array...................................................... 47 7.3 id-cfi address space .................................................. 48 7.4 jedec jesd216b serial flash discoverable parameters (sfdp) space............................................................... 48 7.5 otp address space ..................................................... 49 7.6 registers....................................................................... 50 8. data protection ........................................................... 59 8.1 secure silicon region (otp). .......... ........... ........... ....... 59 8.2 write enable command.......... ............... .............. ......... 59 8.3 block protection ............................................................ 60 8.4 advanced sector protection ......................................... 61 9. commands .................................................................. 66 9.1 command set summary............................................... 67 9.2 identification commands .............................................. 72 9.3 register access commands......................................... 75 9.4 read memory array commands ............. .............. ....... 85 9.5 program flash array commands ................................. 93 9.6 erase flash array commands...................................... 97 9.7 one time program array commands ........................ 102 9.8 advanced sector protection commands .................... 103 9.9 reset commands ....................................................... 109 9.10 embedded algorithm performa nce tables ................. 110 10. data integrity ............................................................. 112 10.1 erase endurance ........................................................ 112 10.2 data retention ..... ....................................................... 112 11. software interface reference .................................. 113 11.1 command summary .................. ................................. 113 12. serial flash discoverable parameters (sfdp) address map ............................................................. 115 12.1 sfdp header field definition s ................................... 116 12.2 device id and common flash interface (id-cfi) address map............................................................... 118 12.3 device id and common flas h interface (id-cfi) aso map ? automotive only ................. .................................... 133 12.4 registers..................................................................... 134 12.5 initial delivery state ........... ......................................... 137 13. ordering information ................................................ 138 14. revision history ........................................................ 140 sales, solutions, and legal information .................... 142 worldwide sales and design supp ort ............ .............. 142 products ....................................................................... 142 psoc? solutions ......................................................... 142 cypress developer community .................................... 142 technical support ................... ..................................... 142 document number: 001-98282 rev. *i page 4 of 142 S25FL127S 1. overview 1.1 general description the cypress S25FL127S device is a flash non-volatile memory product using: ? mirrorbit technology - that stores two data bits in each memory array transistor ? eclipse architecture - that dramatically improves program and erase performance ? 65 nm process lithography this device connects to a host system via a serial peripheral in terface (spi). traditional spi si ngle bit serial input and outp ut (single i/o or sio) is supported as well as optional two bit (dual i/o or dio) and four bit (quad i/o or qio) serial commands. this mul tiple width interface is called spi multi-i/o or mio. the eclipse architecture features a page progr amming buffer that allows up to 128 word s (256 bytes) or 256 words (512 bytes) to be programmed in one operation, resulting in faster effective pr ogramming and erase than prior generation spi program or erase algorithms. executing code directly from flash memory is often called execute- in-place or xip. by using fl-s devices at the higher clock ra tes supported, with qio command , the instruction read transfer rate can match or exceed traditional parallel interface, asynchronou s, nor flash memories while reduci ng signal count dramatically. the S25FL127S product offers a high density coupled with the flex ibility and fast performance required by a variety of embedded applications. it is ideal for code shadowing, xip, and data storage. document number: 001-98282 rev. *i page 5 of 142 S25FL127S 1.2 migration notes 1.2.1 features comparison the S25FL127S device is command set and footprint compatible with prior generation fl-k, fl-p, and fl-s family devices. notes: 1. 256b program page option only for 128 mb and 256-mb density fl-s devices. 2. fl-p column indicates fl129p mio spi device (for 128-mb density). fl128p does not support mio, otp or 4-kb sectors. 3. 64-kb sector erase option only for 128-mb /256-mb density fl-p and fl-s devices. 4. fl-k family devices can erase 4-kb sectors in groups of 32 kb or 64 kb. 5. refer to individual data sheets for further details. table 1. fl generations comparison parameter fl-k fl-p fl-s fl127s technology node 90 nm 90 nm 65 nm 65 nm architecture floating gate mirrorbit mirrorbit eclipse mirrorbit eclipse density 4 mb - 128 mb 32 mb - 256 mb 128 mb, 256 mb, 512 mb, 1 gb 128 mb bus width x1, x2, x4 x1, x2, x4 x1, x2, x4 x1, x2, x4 supply voltage 2.7v - 3.6v 2.7v - 3.6v 2.7v - 3.6v / 1.65v - 3.6v v io 2.7v - 3.6v normal read speed (sdr) 6 mb/s (50 mhz) 5 mb/s (40 mhz) 6 mb/s (50 mhz) 6 mb/s (50 mhz) fast read speed (sdr) 13 mb/s (104 mhz) 13 mb/s (104 mhz) 17 mb/s (133 mhz) 13.5 mb/s (108 mhz) dual read speed (sdr) 26 mb/s (104 mhz) 20 mb/s (80 mhz) 26 mb/s (104 mhz) 27 mb/s (108 mhz) quad read speed (sdr) 52 mb/s (104 mhz) 40 mb/s (80 mhz) 52 mb/s (104 mhz) 54 mb/s (108 mhz) fast read speed (ddr) - - 16 mb/s (66 mhz) - dual read speed (ddr) - - 33 mb/s (66 mhz) - quad read speed (ddr) - - 66 mb/s (66 mhz) - program buffer size 256b 256b 256b / 512b 256b / 512b uniform sector size 4 kb 64 kb / 256 kb 64 kb / 256 kb 64 kb / 256 kb parameter sector size n/a 4 kb 4 kb (option) 4 kb (option) number of parameter sector 0 32 32 (option) 16 (option) sector erase rate (typ.) 135 kb/s (4 kb), 435 kb/s (64 kb) 130 kb/s (64 kb) 30 kb/s (4 kb), 500 kb/s (64 kb / 256 kb) 30 kb/s (4 kb), 500 kb/s (64 kb / 256 kb) page programming rate (typ.) 365 kb/s (256b) 170 kb/s (256b) 1000 kb/s (256b), 1500 kb/s (512b) 650 kb/s (256b), 800 kb/s (512b) otp 768b (3 x 256b) 506b 1024b 1024b advanced sector protection no no yes yes auto boot mode no no yes yes erase suspend/resume yes no yes yes program suspend/ resume yes no yes yes operating temperature - 40c to +85c -40c to +85c / +105c -40c to +85c / +105c -40c to +85c / +105c document number: 001-98282 rev. *i page 6 of 142 S25FL127S 1.2.2 known differences from prior generations 1.2.2.1 error reporting prior generation fl memories either do not have error status bits or do not set them if program or erase is attempted on a prot ected sector. the fl-s family does have error reporting status bits fo r program and erase operations. these can be set when there is an internal failure to program or erase or when there is an attemp t to program or erase a protected sector. in either case the pro gram or erase operation did not complete as requested by the command. 1.2.2.2 secure silicon region (otp) the size and format (address map) of the one time program area is different from prior generat ions. the method for protecting each portion of the otp area is different. for additional details see secure silicon region (otp) on page 59 . 1.2.2.3 configuration register freeze bit the configuration register freeze bit cr1[0], locks the state of the block protection bits as in prior generations. in the fl-s family it also locks the state of the configuration register tbparm bit cr1[2], tbprot bit cr1[5], and the se cure silicon region (otp) area. 1.2.2.4 sector architecture the fl127s has sixteen 4-kbyte sectors that may be located at the top or bottom of ad dress space. other members of the fl-s family and fl-p family have thirty tw o 4-kbyte sectors that may be located at the top or bottom of address space. these smaller parameter sectors may also be removed, leaving al l sectors uniform in size, dependi ng on the selected configurati on (sr2[7]). 1.2.2.5 sector erase commands the command for erasing an 8-kbyte area (t wo 4-kbyte sectors) is not supported. the command for erasing a 4-kbyte sector is supported only for us e on the 4-kbyte parameter sectors at the top or bottom of the device address space. the 4-kbyte erase command will only erase the parameter sectors. the erase command for 64-kbyte sectors is supported when the c onfiguration option for 4-kbyte parameter sectors with 64-kbyte uniform sectors is used. the 64-kbyte erase command may be applied to erase a group of sixteen 4-kbyte sectors. the erase command for a 256-kbyte sector replaces the 64-k byte erase command when the conf iguration option for 256-kbyte uniform sectors is used. 1.2.2.6 deep power down the deep power down (dpd) function is not supported in fl-s family devices. the legacy dpd (b9h) command code is instead used to enable lega cy spi memory controllers, t hat can issue the former dpd command, to access a new bank address register. the bank address register allows spi memory co ntrollers that do not support more than 24 bits of address, the ability to provide higher or der address bits for commands, as needed to access the larger add ress space of the 256-mbit and 512-mbit density fl -s devices. for additional information see extended address on page 47 . 1.2.2.7 hardware reset a separate hardware reset input is provided in packages with gr eater than 8 connections. in 8-connection packages, a new option is provided to replace the hold# / io3 input with an io3 / reset# i nput to allow for hardware reset in small packages. document number: 001-98282 rev. *i page 7 of 142 S25FL127S 1.2.2.8 new features the fl-s family introduces several new features to spi category memories: ? extended address for access to higher memory density. ? autoboot for simpler access to boot code following power up. ? enhanced high performance read commands using mode bits to eliminate the overhead of si o instructions when repeating the same type of read command. ? multiple options for initial read latency (number of dummy cycles) for faster initial access time or higher clock rate read commands. ? automatic ecc for enhanced data integrity. ? advanced sector protection for individually controlling the protection of each sector. this is very similar to the advanced sector protection feature found in several other cypress parallel interface nor memory families. 1.3 glossary bcd binary coded decimal. a value in which eac h 4-bit nibble represents a decimal numeral. command all information transferred between the host system and memory during one period while cs# is low. this includes the instruction (sometimes called an operati on code or opcode) and any required address, mode bits, latency cycles, or data. ecc ecc unit = 16 byte aligned and length data groups in the main flash array and otp array, each of which has its own hidden ecc syndrome to enable error correction on each group. flash the name for a type of electrical erase programmable read only memory (eeprom) that erases large blocks of memory bits in parallel, making the er ase operation much faster than early eeprom. high a signal voltage level v ih or a logic level repr esenting a binary one (1). instruction the 8-bit code indicating the function to be performed by a command (sometimes called an operation code or opcode). the instruction is always the first 8 bits trans ferred from host system to the memory in any command. low a signal voltage level v il or a logic level representing a binary zero (0). lsb (least significant bit) generally the right most bit, with the lowest order of magni tude value, within a group of bits of a register or data value. msb (most significant bit) generally the left most bit, with the hi ghest order of magnitude value, within a group of bits of a register or data value. non-volatile no power is needed to maintain data stored in the memory. opn (ordering part number) the alphanumeric string specifying the me mory device type, density, package, fa ctory non-volatile configuration, etc. used to select the desired device. page 512 bytes or 256 bytes aligned and length group of data. pcb printed circuit board register bit references are in the format: register_name[bit_number] or register_name[bit_range_msb: bit_range_lsb] sector erase unit size; depending on device model and sector locati on this may be 4 kbytes, 64 kbytes or 256 kbytes. write an operation that changes data within volatile or non-vola tile registers bits or non-volatile flash memory. when changing non-volatile data, an erase and reprogramming of any unchanged non-volatile data is done, as part of the operation, such that the non-volatile data is modified by the write operation, in the same way that volatile data is modified ? as a single operation. the non-volatile data appears to the host system to be updated by the single write command, without the need for separate commands for erase and reprogram of adjacent, but unaffected data. document number: 001-98282 rev. *i page 8 of 142 S25FL127S 1.4 other resources 1.4.1 links to software www.cypress.com/software-and-d rivers-cypress-flash-memory 1.4.2 links to application notes www.cypress.com/appnotes 1.4.3 specification bulletins specification bulletins provide informatio n on temporary differences in feature desc ription or parametric variance since the publication of the last full data sheet. contact your local sale s office for details. obtain the latest list of company locatio ns and contact information at: www.cypress.com document number: 001-98282 rev. *i page 9 of 142 S25FL127S hardware interface serial peripheral interface with multiple input / output (spi-mio) many memory devices connect to their host system with separate pa rallel control, address, and data signals that require a large number of signal connections and larger package size. the large number of connections increase power consumption due to so many signals switching and the la rger package increases cost. the s25fl-s family of devices reduces the number of signals for connecti on to the host system by se rially transferring all cont rol, address, and data information over 4 to 6 signals. this reduces the cost of th e memory package, reduce s signal switching power, and either reduces the host connection count or frees host connectors for use in providing other features. the s25fl-s family of devices uses the industry standard single bit serial peripheral interface (spi) and also supports optional extension commands for two bit (dual) and four bit (quad) wide seri al transfers. this multiple width interface is called spi mu lti-i/o or spi-mio. 2. signal descriptions 2.1 input/output summary table 2. signal list signal name type description reset# input hardware reset. the signal has an internal pull-up resistor and should be left unconnected in the host system if not used. sck input serial clock. cs# input chip select. si / io0 i/o serial input for single bit data commands or io0 for dual or quad commands. so / io1 i/o serial output for single bit data commands. io1 for dual or quad commands. wp# / io2 i/o write protect when not in quad mode. io2 in quad mode. the signal has an internal pull-up resistor and may be left unconnected in th e host system if not used for quad commands. hold# / io3 or io3 / reset# i/o hold (pause) serial transfer in single bit or dual data commands. io3 in quad-i/o mode. reset# when enabled by sr2[5]=1 and not in quad-i/o mode, cr1[1 ]=0. or when cs# is high. the signal has an internal pull-up resistor and may be left unconnected in the host system if not used for quad commands. v cc supply power supply. v ss supply ground. nc unused not connected. no device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. the connection may safely be used for routing space for a signal on a printed circuit board (pcb). however, any signal connected to an nc must not have voltage levels higher than v cc . rfu reserved reserved for future use. no device internal signal is currently connected to the package connector but there is potential future use of the connector for a signal. it is recommended to not use rfu connectors for pcb routing channels so that the pcb may take advantage of future enhanced features in comp atible footprint devices. dnu reserved do not use. a device internal signal may be conn ected to the package connector. the connection may be used by cypress for test or other purposes and is not intended for connection to any host system signal. any dnu signal related function will be inactive when the signal is at v il . the signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to v ss . do not use these connections for pc b signal routing channels. do not connect any host system signal to this connection. document number: 001-98282 rev. *i page 10 of 142 S25FL127S 2.2 address and data configuration traditional spi single bit wide commands (single or sio) send in formation from the host to the memory only on the si signal. da ta may be sent back to the ho st serially on the serial output (so) signal. dual or quad output commands send information from the host to the memory only on the si signal. data will be returned to the host as a sequence of bit pairs on io0 and io1 or fo ur bit (nibble) groups on io0, io1, io2 , and io3. dual or quad input/output (i/o) commands send information from the host to the memory as bit pairs on io0 and io1 or four bit (nibble) groups on io0, io1, io 2, and io3. data is returned to the host simila rly as bit pairs on io0 and io1 or four bit (nibb le) groups on io0, io1, io2, and io3. 2.3 hardware reset (reset#) the reset# input provides a hardware method of resetting the device to standby state, ready for receiving a command. when reset# is driven to logic low (v il ) for at least a period of t rp , the device: ? terminates any operation in progress, ? tristates all outputs, ? resets the volatile bits in the configuration register, ? resets the volatile bits in the status registers, ? resets the bank address register to 0, ? loads the program buffer with all 1s, ? reloads all internal configuration information necessary to bring the device to standby mode, ? and resets the internal control unit to standby state. reset# causes the same initialization process as is performed when power comes up and requires t pu time. reset# may be asserted low at an y time. to ensure data in tegrity any operation that was interru pted by a hardware reset should be reinitiated once the device is ready to accept a command sequence. when reset# is first asserted low, the device draws i cc1 (50 mhz value) during t pu . if reset# continues to be held at v ss the device draws cmos standby current (i sb ). reset# has an internal pull-up resistor and should be left unconnected in the host system if not used. the reset# input is not available on all packages options. when not available the reset# input of th e device is tied to the ina ctive state, inside the package. 2.4 serial clock (sck) this input signal provides the synchronization reference for the spi interface. instructions, add resses, or data input are latc hed on the rising edge of the sck signal. data output changes after the falling edge of sck. 2.5 chip select (cs#) the chip select signal indicates when a command for the device is in process and the other sig nals are relevant for the memory device. when the cs# signal is at the logic high state, the dev ice is not selected and all input signals are ignored and all ou tput signals are high impedance. unless an internal program, erase or write registers (wrr) embedded operation is in progress, the device will be in the standby power mode. driving the cs# input to logic low state enables the de vice, placing it in the active power mode. after power-up, a falling edge on cs# is required prior to the start of any command. document number: 001-98282 rev. *i page 11 of 142 S25FL127S 2.6 serial input (si) / io0 this input signal is used to tr ansfer data serially into the de vice. it receives instructions, a ddresses, and data to be progra mmed. values are latched on the rising edge of serial sck clock signal. si becomes io0 - an input and output during dual and quad comm ands for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial sck clock sig nal) as well as shifting out data (on the falling edge of sck) . 2.7 serial output (so) / io1 this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of the serial s ck clock signal. so becomes io1 - an input and output during dual and quad co mmands for receiving addresses, and data to be programmed (values latched on rising edge of serial sck clock signal) as well as shifting out data (on the falling edge of sck. 2.8 write protect (wp#) / io2 when wp# is driven low (v il ), during a wrr command and while the status re gister write disable (srwd) bit of the status register is set to a 1, it is not possibl e to write to the status and configuration registers. this prevents any alteration of the block protect (bp2, bp1, bp0) and tbprot bits of t he status register. as a cons equence, all the data bytes in the memory area that ar e protected by the block protect and tbprot bits, are also hardwar e protected against data modifica tion if wp# is low during a wrr command. the wp# function is not available when the quad mode is enable d (cr[1]=1). the wp# function is replaced by io2 for input and output during quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the sck signal ) as well as shifting out data (on the falling edge of sck). wp# has an internal pull-up resistor; when unconnected, wp# is at v ih and may be left unc onnected in t he host system if not used for quad mode. 2.9 hold (hold#) / io3 / reset# the hold (hold#) signal is used to pause any serial communicati ons with the device without deselecting the device or stopping t he serial clock. the hold# input and function is availa ble when enabled by a conf iguration bit sr2[5] =0. to enter the hold condition, the device must be selected by driv ing the cs# input to the logic low state. it is recommended tha t the user keep the cs# input low state during the entire duration of the hold condition. this is to ensure that the state of the int erface logic remains unchanged from the moment of entering the hold c ondition. if the cs# input is driven to the logic high state whil e the device is in the hold condition, the inte rface logic of the device will be reset. to restart communication with the device, it is necessary to drive hold# to the logic high state while driving th e cs# signal into the logic low state. this prevents the devic e from going back into the hold condition. the hold condition starts on the falling edge of the hold (hold#) signal, provided that this coincides with sck being at the lo gic low state. if the falling edge does not coincide with the sck signal bei ng at the logic low state, the hold condition starts whenev er the sck signal reaches the logic low state. taking the hold# signal to the logic low state does not terminate any write, program or erase operation that is currently in progress. during the hold condition, so is in high impedance and both the si and sck input are don't care. the hold condition ends on the rising edge of the hold (hold#) si gnal, provided that this coincides with the sck signal being a t the logic low state. if the rising edge does not coincide with the sck signal being at the logic low state, the hold condition ends whenever the sck signal reaches the logic low state. the hold# function is not available when the quad mode is enab led (cr1[1] =1). the hold function is replaced by io3 for input and output during quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the sck signal) as well as shifting out data (on the falling edge of sck. a configuration bit sr2[5] may be set to 1 to replace the hold# / io3 functions with the io3 / reset# functions. then the io3 / reset# may be used to initiate the hardware reset function. the io3 / reset# input is only treated as reset# when the device is not in quad-i/o mode, cr1[1] = 0, or when cs# is high. document number: 001-98282 rev. *i page 12 of 142 S25FL127S when quad i/o mode is in use, cr1[1]=1, and the device is se lected with cs# low, the io3 / reset# is used only as io3 for information transfer. when cs# is high, t he io3 / reset# is not in use for information transfer and is used as the reset# input . by conditioning the reset operation on cs# high during quad mode, the reset function remains available during quad mode. when the system enters a reset co ndition, the cs# signal must be driven high as part of t he reset process and the io3 / reset# signal is driven low. when cs # goes high the io3 / reset# input transitions from being io3 to being the reset# input. the reset condition is then detected when cs# remains high and the io3 / reset# signal remains low for t rp . the hold#/io3 or io3/reset# signals have an internal pull-up resistor and may be left unconnected in the host system if not use d for quad mode or the reset function. when quad mode is enabled, io3 / reset# is ignored for t cs following cs# going high. this allows some time for the memory or host system to actively drive io3 / reset# to a valid level fo llowing the end of a transfer. following the end of a quad i/o re ad the memory will actively drive io3 high before disabling the output during t dis . following a transfer in which io3 was used to transfer data to the memory, e.g. the q pp command, the host system is resp onsible for driving io3 high bef ore disabling the host io3 out put. this will ensure that io3 / reset is not left floating or being pulled slowly to high by the internal or an external passive pu ll-up. thus, an unintended reset is not trigger ed by the io3 / reset# not being reco gnized as high bef ore the end of t rp . once io3 / reset# is high the memory or host system can stop dr iving the signal. t he integrated pull-up on io3 will then hold io3 high unless the ho st system actively drives io3 / reset# to initiate a reset. note that io3 / reset# cannot be shared by more than one spi-mio memory if any of t hem are operating in quad i/o mode as io3 being driven to or from one selected memory may look like a rese t signal to a second not selected memory sharing the same io3 / reset# signal. see section 5.3.3 io3 / reset # input initiat ed hardware (warm) reset on page 33 for the io3 / reset timing. figure 1. hold mode operation 2.10 voltage supply (v cc ) v cc is the voltage source for all device internal logic. it is th e single voltage used for all device internal functions including read, program, and erase. the voltage may vary from 2.7v to 3.6v. 2.11 supply and signal ground (v ss ) v ss is the common voltage drain and ground reference for the device core, input signal receivers, and output drivers. 2.12 not connected (nc) no device internal signal is connected to the package connector no r is there any future plan to use the connector for a signal. the connection may safely be used for routing space for a signal on a printed circuit board (pcb). ho wever, any signal connected to an nc must not have voltage levels higher than v cc . 2.13 reserved for future use (rfu) no device internal signal is currently connected to the package connector but is ther e potential future use of the connector. i t is recommended to not use rfu connectors for pcb routing channe ls so that the pcb may take advantage of future enhanced features in compatib le footprint devices. cs# sclk hold# si_or_io_(during_input) so_or_io_(internal) so_or_io_(external) valid input don't care valid input don't care valid input a b c d e a b b c d e hold condition standard use hold condition non-standard use document number: 001-98282 rev. *i page 13 of 142 S25FL127S 2.14 do not use (dnu) a device internal signal may be connected to the package connecto r. the connection may be used by cypress for test or other purposes and is not intended for connection to any host system signal. any dnu signal related function will be inactive when th e signal is at v il . the signal has an inte rnal pull-down resistor and may be left unconnected in t he host system or may be tied to v ss . do not use these connections for pcb signal routing channels. do not connect any host system signal to these connections. 2.15 block diagrams figure 2. bus master and memory devices on the spi bus - single bit data path figure 3. bus master and memory devices on the spi bus - dual bit data path reset# wp# si so sck cs2# cs1# cs1# spi bus master fl127s flash fl127s flash cs2# sck si so reset# wp# reset# wp# io1 io0 sck cs2# cs1# spi bus master reset# wp# io1 io0 sck cs2# cs1# fl127s flash fl127s flash document number: 001-98282 rev. *i page 14 of 142 S25FL127S figure 4. bus master and memory devi ces on the spi bus - quad bit data path reset# io2 io1 sck cs2# cs1# cs2# sck reset# cs1# spi bus master fl127s flash fl127s flash io2 io1 io3 io0 io3 io0 document number: 001-98282 rev. *i page 15 of 142 S25FL127S 3. signal protocols 3.1 spi clock modes 3.1.1 single data rate (sdr) the s25fl-s family of devices can be driven by an embedded microc ontroller (bus master) in either of the two following clocking modes. ? mode 0 with clock polarity (cpol) = 0 and, clock phase (cpha) = 0 ? mode 3 with cpol = 1 and, cpha = 1 for these two modes, input data into the device is always latched in on the rising edge of the sck signal and the output data i s always available from the falling edge of the sck clock signal. the difference between the two modes is t he clock polarity when the bus master is in standby mode and not transferring any data . ? sck will stay at logic low state with cpol = 0, cpha = 0 ? sck will stay at logic high state with cpol = 1, cpha = 1 figure 5. spi modes supported timing diagrams throughout the remainder of the document are g enerally shown as both mode 0 and 3 by showing sck as both high and low at the fall of cs#. in some cases a timing diagram ma y show only mode 0 with sck low at the fall of cs#. in such a case, mode 3 timing simply means clock is high at the fall of cs# so no sck rising edge set up or hold time to the falling edge of cs# is needed for mode 3. sck cycles are measured (counted) from one falling edge of sc k to the next falling edge of sck. in mode 0 the beginning of the first sck cycle in a command is measured from the falling edge of cs# to the first falling edge of sck because sck is already l ow at the beginning of a command. 3.2 command protocol all communication between the host system and s25fl-s family of memory devices is in the form of units called commands. all commands begin with an instruction that selects the type of information transfer or device operation to be performed. comma nds may also have an address, instruction modifier, latency period, da ta transfer to the memory, or data transfer from the memory. all instruction, address, and data information is transferred serially between the host system and memory device. all instructions are transferred from host to memory as a single bit serial sequence on the si signal. single bit wide commands may provide an address or data sent only on the si signal. data may be sent back to the host serially on the so signal. dual or quad output commands provide an address sent to the memo ry only on the si signal. data will be returned to the host as a sequence of bit pairs on io0 and io1 or four bit (nibble) groups on io0, io1, io2, and io3. dual or quad input/output (i/o) commands provide an address sent from the host as bit pairs on io0 and io1 or, four bit (nibble ) groups on io0, io1, io2, and io3. data is returned to the host similarly as bit pairs on io0 and io1 or, four bit (nibble) grou ps on io0, io1, io2, and io3. p ol=0_cpha=0_sclk p ol=1_cpha=1_sclk cs# si so msb msb document number: 001-98282 rev. *i page 16 of 142 S25FL127S commands are structured as follows: ? each command begins with cs# going low and ends with cs# returning high. the memory device is selected by the host driving the chip select (cs#) signal low throughout a command. ? the serial clock (sck) marks the transfer of each bit or group of bits between the host and memory. ? each command begins with an eight bit (byte) instruction. t he instruction is always presented only as a single bit serial sequence on the serial input (si) signal with one bit tran sferred to the memory device on each sck rising edge. the instruction selects the type of information transfer or device operation to be performed. ? the instruction may be stand alone or may be followed by addres s bits to select a byte location within one of several address spaces in the device. the instruction determines t he address space used. the address may be either a 24-bit or a 32-bit address. the address transfers occur on sck rising edge. ? the width of all transfers following the instruction are determ ined by the instruction sent. following transfers may continue to be single bit serial on only the si or serial output (so) signals, they may be done in two bit groups per (dual) transfer on the io0 and io1 signals, or they may be done in 4 bit groups per (quad) transfer on the io0-io3 signals. within the dual or quad groups the least significant bit is on io0. more signi ficant bits are placed in significance order on each higher numbered io signal. single bits or parallel bit groups are transferred in most to least significant bit order. ? some instructions send an instruction modifier called mode bi ts, following the address, to indicate that the next command will be of the same type with an implied, rather than an exp licit, instruction. the next co mmand thus does not provide an instruction byte, only a new address and mode bits. this re duces the time needed to send each command when the same command type is repeated in a sequence of comma nds. the mode bit transfers occur on sck rising edge. ? the address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before read data is returned to the host. ? write data bit transfers occur on sck rising edge. ? sck continues to toggle duri ng any read access latency pe riod. the latency may be zero to several sck cycles (also referred to as dummy cycles). at the end of the read latency cycl es, the first read data bits are driven from the outputs on sck falling edge at the end of the last read latency cycle. the first read data bits are consi dered transferred to the ho st on the following sck rising edge. each following transfer occurs on the next sck rising edge. ? if the command returns read data to the host, the device continues sending data transfers until the host takes the cs# signal high. the cs# signal can be driven high after any tr ansfer in the read data sequence. this will terminate the command. ? at the end of a command that does not return data, the host dr ives the cs# input high. the cs# signal must go high after the eighth bit, of a stand alone instruction or, of the last write data byte that is transferred. that is, the cs# signal must be driven high when the number of clock cycles after cs# signal was driven low is an exac t multiple of eight cycles. if the cs# signal does not go high exactly at the eight sck cycle boun dary of the instruction or writ e data, the command is rejected and not executed. ? all instruction, address, and mode bits are shifted into the device with the most signif icant bits (msb) first. the data bits a re shifted in and out of the device msb first. all data is transferred in byte units with the lowest address byte sent first. following bytes of data are sent in lowest to high est byte address order i.e. the byte address increments. ? all attempts to read the flash memory array during a progr am, erase, or a write cycle (e mbedded operations) are ignored. the embedded operation will continue to exec ute without any affect. a very limited se t of commands are accepted during an embedded operation. these are discussed in the individual command descriptions. ? depending on the command, the time for execution varies. a command to read status information from an executing command is available to determine when the command co mpletes execution and whether the command was successful. document number: 001-98282 rev. *i page 17 of 142 S25FL127S 3.2.1 command sequence examples figure 6. stand alone instruction command figure 7. single bit wide input command figure 8. single bit wide output command figure 9. single bit wide i/o command without latency figure 10. single bit wide i/o command with latency cs# sck si so phase instruction cs# sck si so phase input data instruction cs# sck si so phase data 1 data 2 instruction cs# sck si so phase instruction address data 1 data 2 cs# sck si so phase address dummy cyles data 1 instruction document number: 001-98282 rev. *i page 18 of 142 S25FL127S figure 11. dual output command figure 12. quad output command without latency figure 13. dual i/o command figure 14. quad i/o command additional sequence diagrams, specific to each command, are provided in section 9. commands on page 66 . cs# sck io0 io1 phase address 6 dummy data 1 instruction data 2 cs# sck io0 io1 phase address data 1 instruction io2 io3 data 2 data 3 data 5 data 4 cs# sck io0 io1 phase address dummy data 1 instruction data 2 mode cs# sck io0 io1 phase address dummy d1 instruction io2 io3 mode d2 d3 d4 document number: 001-98282 rev. *i page 19 of 142 S25FL127S 3.3 interface states this section describes the input and output signal levels as related to the spi interface behavior. legend z = no driver - floating signal hl = host driving v il hh = host driving v ih hv = either hl or hh x = hl or hh or z ht = toggling between hl and hh ml = memory driving v il mh = memory driving v ih mv = either ml or mh table 3. interface states summary with separate reset interface state v cc reset# sck cs# hold# / io3 wp# / io2 so / io1 si / io0 power-off document number: 001-98282 rev. *i page 23 of 142 S25FL127S 3.3.9 single latency (dummy) cycle read commands may have zero to several late ncy cycles during which read data is read fr om the main flash memory array before transfer to the host. the number of latency cycles are determi ned by the latency code in the configuration register (cr[7:6]). during the latency cycles, the host keeps reset# high, cs# low, and ho ld# high. the write protect (w p#) signal is ignored. the host may drive the si signal during t hese cycles or the host may leave si floating. th e memory does not use any data driven on si / i/ o0 or other i/o signals during the latency cycles. in dual or quad read commands, the host must stop driving the i/o signals on th e falling edge at the end of the last latency cycle. it is recomm ended that the host stop driving i/o signals during latency cycl es so that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. t his prevents driver conflict between host and memory when the signal direction changes. the memory does not drive the serial output (so) or i/o signals during the latency cycles. the next interface state depends on the comm and structure i.e. the number of latency cycles, and whether the read is single, du al, or quad width. 3.3.10 single output cycle - memory to host transfer several commands transfer information back to the host on the si ngle serial output (so) signal. the host keeps reset# high, cs# low, and hold# high. the write protect (wp#) signal is ignored. the memory ignores the serial input (si) signal. the memory drives so with data. the next interface state continues to be single output cycle until the host returns cs# to high ending the command. 3.3.11 dual input cycle - host to memory transfer the read dual i/o command transfers two address or mode bits to the memory in each cycle. the host keeps reset# high, cs# low, hold# high. the write protect (wp#) signal is igno red. the host drives address on si / io0 and so / io1. the next interface st ate following the delivery of address a nd mode bits is a dual latency c ycle if there are latency cycles ne eded or dual output cycle if no latency is required. 3.3.12 dual latency (dummy) cycle read commands may have zero to several late ncy cycles during which read data is read fr om the main flash memory array before transfer to the host. the number of latency cycles are determi ned by the latency code in the configuration register (cr[7:6]). during the latency cycles, the host keeps reset# high, cs# low, and ho ld# high. the write protect (w p#) signal is ignored. the host may drive the si / io0 and so / io1 signals during these cycles or the host may leave si / io0 and so / io1 floating. the memory does not use any data driven on si / io0 a nd so / io1 during the latency cycles. the ho st must stop driving si / io0 and so / io1 on the falling edge at the end of the last latency cycle. it is recommended that the host stop driving them during all latency cycles so that there is sufficient time for the host drivers to turn off before the memory begi ns to drive at the end of the latency cycl es. this prevents driver conflict between host and memory when the signal direction changes. the memory does not drive the si / io0 and so / io1 signals during the latency cycles. the next interface state fo llowing the last la tency cycle is a du al output cycle. 3.3.13 dual output cycle - memory to host transfer the read dual output and read dual i/o return data to the host two bits in each cycle. the host keeps reset# high, cs# low, and hold# high. the write protect (wp#) signal is ignored. the memo ry drives data on the si / io0 and so / io1 signals during the dual output cycles. the next interface state continues to be dual output cycl e until the host returns cs# to high ending the command. 3.3.14 qpp or qor address input cycle the quad page program and quad output read commands send addres s to the memory only on io0. the other io signals are ignored because the device must be in quad mode for these commands thus the hold and write protec t features are not active. the host keeps reset# high, cs # low, and drives io0. for qpp the next interface state following the delivery of address is the quad input cycle. for qor the next interface state following ad dress is a quad latency cycle if there are latency cycles needed or quad output cycle if no latency is required. document number: 001-98282 rev. *i page 24 of 142 S25FL127S 3.3.15 quad input cycle - host to memory transfer the quad i/o read command transfers four address or mode bits to the memory in each cycle. the quad page program command transfers four data bits to the memory in each cycle. the host keeps reset# high, cs# low, and drives the io signals. for quad i/o read the next interface state fo llowing the delivery of address and mode bits is a quad latency cycle if there are latency cycles needed or quad output cycle if no latency is requi red. for quad page program the host returns cs# high following the delivery of data to be programmed an d the interface returns to standby state. 3.3.16 quad latency (dummy) cycle read commands may have zero to several late ncy cycles during which read data is read fr om the main flash memory array before transfer to the host. the number of latency cycles are determi ned by the latency code in the configuration register (cr[7:6]). during the latency cycles, the host keeps reset# high, cs# low. the host may drive the io signals during these cycles or the host may leave the io floating. the memory does not use any data driven on io duri ng the latency cycles. the hos t must stop driving the io signals on the falling edge at the end of the last latency cycle. it is recommended that the host stop driving them during all latency cycles so that there is sufficien t time for the host drivers to tu rn off before the memory begins to drive at the end of the la tency cycles. this prevents driver conflict between host and memory when the signal direction changes. the memory does not drive the io signals during the latency cycles. the next interface state following the la st latency cycle is a quad output cycle. 3.3.17 quad output cycle - memory to host transfer the quad output read and quad i/ o read return data to the host four bits in each cycle. the host keeps reset# high, and cs# low. the memory drives data on io0-io3 signals during the quad output cycles. the next interface state continues to be quad output c ycle until the host returns cs# to high ending the command. 3.4 configuration register effects on the interface the configuration register bits 7 and 6 (cr1[7:6]) select the la tency code for all read commands . the latency code selects the number of mode bit and latency cycl es for each type of instruction. the configuration register bit 1 (cr1[1]) selects whether quad mode is enabled to ignore hold# and wp# and allow quad page program, quad output read, and quad i/o read commands. 3.5 data protection some basic protection against unintended changes to stored data are provided and controlled purel y by the hardware design. thes e are described below. other software managed protection methods are discussed in the section , software interface on page 47 . 3.5.1 power-up when the core supply voltage is at or below the v cc (low) voltage, the device is consider ed to be powered off. the device does not react to external signals, and is prevented from performing any program or erase operation. program and erase operations contin ue to be prevented during the power-on reset (por) because no comma nd is accepted until the exit from por to the interface standby state. 3.5.2 low power when v cc is less than v cc (cut-off) the memory device will ignore commands to ensure that program and erase operations can not start when the core supply volta ge is out of the operating range. 3.5.3 clock pulse count the device verifies that all program, eras e, and write registers (wrr) commands consis t of a clock pulse co unt that is a multip le of eight before executing them. a comm and not having a multiple of 8 clock pulse count is ignored and no error status is set for t he command. document number: 001-98282 rev. *i page 25 of 142 S25FL127S 4. electrical specifications 4.1 absolute maximum ratings notes: 1. see input signal overshoot on page 25 for allowed maximums during signal transition. 2. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 3. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions abov e those indicated in the operational sections of this data sheet is not implied. ex posure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 4.2 operating ranges operating ranges define those limit s between which the functionalit y of the device is guaranteed. 4.2.1 temperature ranges industrial plus operating and performance parameters will be dete rmined by device characterization and may vary from standard industrial temperature range devices as currently shown in this specification. 4.2.2 power supply voltage v cc 2.7v to 3.6v 4.2.3 input sign al overshoot during dc conditions, input or i/o signals should remain equal to or between v ss and v cc . during voltage transitions, inputs or i/os may overshoot v ss to ?2.0v or overshoot to v cc +2.0v, for periods up to 20 ns. figure 15. maximum negative overshoot waveform table 6. absolute maximum ratings storage temperature plastic packages -65c to +150c ambient temperature with power applied -65c to +125c v cc -0.5v to +4.0v input voltage with respect to ground (v ss ) (note 1) -0.5v to +(v cc + 0.5v) output short circuit current (note 2) 100 ma parameter symbol device spec unit min max ambient temperature t a industrial (i) ?40 +85 c industrial plus (v) ?40 +105 automotive, aec-q100 grade 3 (a) ?40 +85 automotive, aec-q100 grade 2 (b) ?40 +105 v il - 2.0v 20 ns 20 ns 20 ns document number: 001-98282 rev. *i page 26 of 142 S25FL127S figure 16. maximum positive overshoot waveform 4.3 power-up and power-down the device must not be selected at power-up or power- down (that is, cs# must follo w the voltage applied on v cc ) until v cc reaches the correct value as follows: ? v cc (min) at power-up, and then for a further delay of t pu ? v ss at power-down a simple pull-up resistor (generally of the order of 100 k ) on chip select (cs#) can usually be used to insure safe and proper power-up and power-down. the device ignores all instructions until a time delay of t pu has elapsed after the moment that v cc rises above the minimum v cc threshold. see figure 17, power-up on page 27 . however, correct operation of th e device is not guaranteed if v cc returns below v cc (min) during t pu . no command should be sent to the device until the end of t pu . the device draws i por during t pu . after power-up (t pu ), the device is in standby mode, draws cmos standby current (i sb ), and the wel bit is reset. during power-down or voltage drops below v cc (cut-off), the voltage must drop below v cc (low) for a period of t pd for the part to initialize correctly on power-up. see figure 18, power-down and voltage drop on page 27 . if during a voltage drop the v cc stays above v cc (cut-off) the part will stay initiali zed and will work correctly when v cc is again above v cc (min). in the event power-on reset (por) did not complete corre ctly after power up, the assert ion of the reset# signal or re ceiving a softwa re reset command (reset) will restart the por process. normal precautions must be taken for supply rail decoupling to stabilize the v cc supply at the device. each device in a system should have the v cc rail decoupled by a suitable capacitor close to the pa ckage supply connection (this ca pacitor is generally of the order of 0.1 f). table 7. power-up/power-down voltage and timing symbol parameter min max unit v cc (min) v cc (minimum operation voltage) 2.7 v v cc (cut-off) v cc (cut 0ff where re-initialization is needed) 2.4 v v cc (low) v cc (low voltage for initialization to occur) 1.0 v t pu v cc (min) to read operation 300 s t pd v cc (low) time 1.0 s v ih v cc + 2.0v 20 ns 20 ns 20 ns document number: 001-98282 rev. *i page 27 of 142 S25FL127S figure 17. power-up figure 18. power-down and voltage drop (max) (min) v cc t pu full device access time v cc v cc t pd (max) (min) v cc t pu device access allowed time v cc v cc no device access allowed (cut-off) v cc (low) v cc document number: 001-98282 rev. *i page 28 of 142 S25FL127S 4.4 dc characteristics applicable within operating ranges. notes: 1. typical values are at t ai = 25c and v cc = 3v. 2. output switching current is not included. 4.4.1 active power and standby power modes the device is enabled and in the active power mode when chip se lect (cs#) is low. when cs# is high, the device is disabled, but may still be in an active power mode until all program, erase, and write operations have complete d. the device then goes into t he standby power mode, and powe r consumption drops to i sb . table 8. dc characteristics symbol parameter test conditions min typ (1) max unit v il input low voltage -0.5 0.2 x v cc v v ih input high voltage 0.7 x v cc v cc + 0.4 v v ol output low voltage i ol = 1.6 ma, v cc = v cc min 0.15 x v cc v v oh output high voltage i oh = ?0.1 ma 0.85 x v cc v i li (industrial) input leakage current v cc = v cc max, v in = 0 to v il max or v ih , cs# = v ih 2 a i lo (industrial) output leakage current v cc = v cc max, v in = v ih or v il 2 a i li (industrial plus) input leakage current v cc = v cc max, v in = 0 to v il max or v ih , cs# = v ih 4 a i lo (industrial plus) output leakage current v cc = v cc max, v in = v ih or v il 4 a i cc1 active power supply current (read) serial @50 mhz serial @108 mhz quad @108 mhz outputs unconnected during read data return (2) 16 24 47 ma i cc2 active power supply current (page program) cs# = v cc 50 ma i cc3 active power supply current (wrr) cs# = v cc 50 ma i cc4 active power supply current (se) cs# = v cc 50 ma i cc5 active power supply current (be) cs# = v cc 50 ma i sb (industrial) standby current reset#, cs# = v cc ; si, sck = v cc or v ss , industrial temp 70 100 a i sb (industrial plus) standby current reset#, cs# = v cc ; si, sck = v cc or v ss , industrial plus temp 70 300 a i por power on reset current reset#, cs# = v cc ; si, sck = v cc or v ss 63 ma document number: 001-98282 rev. *i page 29 of 142 S25FL127S 5. timing specifications 5.1 key to switching waveforms figure 19. waveform element meanings figure 20. input, output, and timing reference levels input symbol output valid at logic high or low valid at logic high or low high impedance any change permitted logic high logic low valid at logic high or low valid at logic high or low high impedance changing, state unknown logic high logic low v io + 0.4v 0.7 x v cc 0.2 x v cc - 0.5v timing reference level 0.5 x v cc 0.85 x v cc 0.15 x v cc input levels output levels document number: 001-98282 rev. *i page 30 of 142 S25FL127S 5.2 ac test conditions figure 21. test setup notes: 1. output high-z is defined as the point where data is no longer driven. 2. input slew rate: 1.5 v/ns. 3. ac characteristics tables assume clock and data signals have the same slew rate (slope). 5.2.1 capacitance characteristics note: 1. parameter values are not 100% tested. for more info rmation on capacitance, please consult the ibis models. table 9. ac measurement conditions symbol parameter min max unit c l load capacitance 30 pf input rise and fall times 2.4 ns input pulse voltage 0.2 x v cc to 0.8 v cc v input timing ref voltage 0.5 v cc v output timing ref voltage 0.5 v cc v table 10. capacitance parameter test conditions min max unit c in input capacitance (a pplies to sck, cs#, reset#) 1 mhz 8 pf c out output capacitance (applies to all i/o) 1 mhz 8 pf device under te s t c l document number: 001-98282 rev. *i page 31 of 142 S25FL127S 5.3 reset 5.3.1 power-on (cold) reset the device executes a power-on reset (por) process until a time delay of t pu has elapsed after the moment that v cc rises above the minimum v cc threshold. see figure 17 on page 27 , table 7 on page 26 , and figure 22 on page 31 . the device must not be selected (cs# to go high with v cc ) during power-up (t pu ), i.e. no commands may be sent to the device until the end of t pu . the io3 / reset# signal functions as the reset# input when cs# is high for more than t rp time or when quad mode is not enabled cr1v[1]=0. reset# is ignored during por. if reset # is low during por and remains low through and beyond the end of t pu , cs# must remain high until t rh after reset# returns high. reset# must return high for greater than t rs before returning low to initiate a hardware reset. figure 22. reset low at the end of por figure 23. reset high at the end of por figure 24. por followed by hardware reset vcc reset# cs# if reset# is low at tpu end cs# must be high at tpu end tpu trh vcc reset# cs# if reset# is high at tpu end cs# may stay high or go low at tpu end tpu tpu vcc reset# cs# trs tpu tpu document number: 001-98282 rev. *i page 32 of 142 S25FL127S 5.3.2 separate reset# input in itiated hardware (warm) reset when the reset # input transitions from v ih to v il for > t rp the device will reset register states in the same manner as power-on reset but, does not go through the full reset process that is pe rformed during por. the hardware reset process requires a perio d of t rph to complete. if the por proce ss did not complete correctly for any reason during power-up (t pu ), reset# going low will initiate the full por process instead of the hardware reset process and will require t pu to complete the por process. a separate reset# input is available only in the soic16 and bg a package options. the reset# input has an internal pull-up to v cc and should be left unconnected if not used. the reset command is independent of the state of reset#. if reset# is high or unconnected, and the reset instruction is i ssued, the device will perform software reset. the reset# input provides a hardware method of re setting the flash memory device to standby state. ? reset# must be high for t rs following t pu or t rph , before going low again to initiate a hardware reset. ? when reset# is driven low for at least a minimum period of time (t rp ), the device terminates any operation in progress, makes all outputs high impedance, and ignores all read/write commands for the duration of t rph . the device resets the interface to standby state. ? if cs# is low at the time reset# is asserted, cs# must return high during t rph before it can be asserted low again after t rh . notes: 1. reset# low is ignored during power-up (t pu ). if reset# is asserted during the end of t pu , the device will remain in the reset state and t rh will determine when cs# may go low. 2. sum of t rp and t rh must be equal to or greater than t rph . figure 25. separate reset# input initiated hardware reset table 11. hardware reset parameters parameter description limit time unit t rs reset setup -prior reset end and reset# high before reset# low min 50 ns t rph reset pulse hold - reset# low to cs# low min 35 s t rp reset# pulse width min 200 ns t rp reset# pulse width (only when autoboot enabled) max 5 s t rh reset hold - reset# high before cs# low min 50 ns reset# cs# any prior reset trs trp trh trh trph trph document number: 001-98282 rev. *i page 33 of 142 S25FL127S 5.3.3 io3 / reset# input initiated hardware (warm) reset the io3 / reset# signal functions as a reset# input when enabled by sr2[5]=1 and cs# is high for more than t cs time or when quad mode is not enabled (cr1v[1]=0). the io3 reset# input provides a hardware method of resetting the flash memory device to standby state. the io 3 / reset# input has an internal pull-up to v cc and may be left unconnected if quad mode is not used. when the io3 / reset# feature and quad mode are both enabled, io3 / reset# is ignored for t cs following cs# going high, to avoid an unintended reset operation. this allows some time for th e memory or host system to actively drive io3 / reset# to a va lid level following the end of a transfer. follo wing the end of a quad i/o read the memory will actively drive io3 high before disa bling the output during t dis . following a transfer in which io3 was used to trans fer data to the memory, e.g. the qpp command, the host system is responsible for driving io3 high before disabling the host io3 output. the int egrated pull-up on io3 will then hold i o3 until the host system active ly drives io3 / reset# to initiate a reset. if cs# is driven low to start a new command, io3 / reset# is used as io3. when the device is not in quad mode or when cs# is high, an d the io3 / reset# transitions from v ih to v il for > t rp , the device terminates any operation in progress, makes all outputs high im pedance, ignores all read/write commands and resets the interfac e to standby state. the hardware re set process requires a period of t rph to complete. during t rph , the device will reset register states in the same manner as power-on reset but, does not go through the full reset process that is performed during por. if the por process did not complete correctly for any reason during power-up (t pu ), reset# going low for t rp will initiate the full por process instead of the hardware reset process and will require t pu to complete the por process. io3 / reset# must be high for t rs following t pu or t rph , before going low again to initiate a hardware reset. if quad mode is not enabled, and if cs# is low at the time io 3 / reset# is asserted low, cs# must return high during t rph before it can be asserted low again after t rh . the reset command is independent of the st ate of reset#. if io3 / reset# is high or unconnected, and t he reset instruction is issued, the device will perform software reset. notes: 1. io3 / reset# low is ignored during power-up (t pu ). if reset# is asserted during the end of t pu , the device will remain in the reset state and t rh will determine when cs# may go low. 2. if quad mode is enabled, io3 / reset# low is ignored during t cs. 3. sum of t rp and t rh must be equal to or greater than t rph . figure 26. hardware reset when quad mode is not enabled and io3 / reset# is enabled figure 27. hardware reset when quad mode and io3 / reset# are enabled table 12. hardware reset parameters parameter description limit time unit t rs reset setup -prior reset end and reset# high before reset# low min 50 ns t rph reset pulse hold - reset# low to cs# low min 35 s t rp reset# pulse width min 200 ns t rp reset# pulse width (only wh en autoboot enabled) max 5 s t rh reset hold - reset# high be fore cs# low min 50 ns io3_reset# cs# any prior reset trs trp trh trh trph trph io3_reset# cs# reset pulse prior access using io3 for data trp trh trph tcs tdis document number: 001-98282 rev. *i page 34 of 142 S25FL127S 5.4 ac characteristics notes: 1. only applicable as a constraint for wrr instruction when srwd is set to a 1. 2. full v cc range (2.7 - 3.6v) and cl = 30 pf. 3. regulated v cc range (3.0 - 3.6v) and cl = 30 pf. 4. regulated v cc range (3.0 - 3.6v) and cl = 15 pf. 5. 10% duty cycle is supported for frequencies 50 mhz. 6. output high -z is defined as the point where data is no longer driven. 7. t cs and t dis require additional time when the reset feature and quad mode are enabled (cr2v[5]=1 and cr1v[1]=1). table 13. ac characteristics symbol parameter min typ max unit f sck, r sck clock frequency for read and 4read instructions dc 50 mhz f sck, c sck clock frequency for single commands as shown in table 36, S25FL127S command set (sorted by function) on page 68 (4) dc 108 mhz f sck, c sck clock frequency for the following dual and quad commands: dor, 4dor, qor, 4qor, dior, 4dior, qior, 4qior dc 108 mhz f sck, qpp sck clock frequency for the qpp, 4qpp commands dc 80 mhz p sck sck clock period 1/ fsck t wh , t ch clock high time (5) 50% psck -5% 50% psck +5% ns t wl , t cl clock low time (5) 50% psck -5% 50% psck +5% ns t crt , t clch clock rise time (slew rate) 0.1 v/ns t cft , t chcl clock fall time (slew rate) 0.1 v/ns t cs cs# high time (read instructions) cs# high time (read instructions when reset feature and quad mode are both enabled) cs# high time (program/erase instructions) 10 20 (7) 50 ns t css cs# active setup time (relative to sck) 3 ns t csh cs# active hold time (relative to sck) 3 ns t su data in setup time 1.5 ns t hd data in hold time 2 ns t v clock low to output valid 1 8.0 (2) 7.65 (3) 6.5 (4) ns t ho output hold time 2 ns t dis output disable time (6) 8ns output disable time (when reset feature and quad mode are both enabled) 20 (7) ns t wps wp# setup time 20 (1) ns t wph wp# hold time 100 (1) ns t hlch hold# active setup time (relative to sck) 3 ns t chhh hold# active hold time (relative to sck) 3 ns t hhch hold# non active setup time (relative to sck) 3 ns t chhl hold# non active hold time (relative to sck) 3 ns t hz hold# enable to output invalid 8 ns t lz hold# enable to output valid 8 ns document number: 001-98282 rev. *i page 35 of 142 S25FL127S 5.4.1 clock timing figure 28. clock timing 5.4.2 input / output timing figure 29. spi single bit input timing figure 30. spi single bit output timing v il max v ih min tch tcrt tcft tcl v cc / 2 p sck cs# sck si so msb in lsb in tcss tcss tcsh tcsh tcs tsu thd cs# sck si so msb out lsb out tcs tlz tho tv tdis document number: 001-98282 rev. *i page 36 of 142 S25FL127S figure 31. spi mio timing figure 32. hold timing figure 33. wp# input timing cs# sck io msb in lsb in . msb out . lsb out tcsh tcss tcss tsu thd tlz tho tcs tdis tv cs# sck hold# si_or_io_(during_input) so_or_io_(during_output) a b b c d e thz tlz thz tlz tchhl tchhl thlch tchhh tchhh thhch thhch thlch hold condition standard use hold condition non-standard use cs# wp# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 wrr instruction input data twps twph document number: 001-98282 rev. *i page 37 of 142 S25FL127S 6. physical interface note: refer to table 2, signal list on page 9 for signal descriptions. 6.1 soic 8-lead package 6.1.1 soic-8 connection diagram figure 34. 8-pin plastic small outline package (so) note: 1. lead 7 hold# / io3 or io3 / reset# function depends on the selected configuration, if the io3 / reset# function is used, the host system should actively or passively pull-up the io3 / reset# connection when quad mode is not enabled, or when cs# is high and a reset operation is not i ntended. table 14. model specific connections reset# / rfu reset# or rfu - some device models bond this connector to the device reset# signal, other models bond the reset# signal to vcc within the package leaving this package connector unconnected. 1 2 3 4 8 7 6 5 cs# so / io1 wp# / io2 gnd si / io0 clk hold# / io3 or io3 / reset# vcc soic document number: 001-98282 rev. *i page 38 of 142 S25FL127S 6.1.2 soic 8 physical diagram figure 35. s0c008 ? 8-lead plastic small outline package (208-mil body width) sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date 5.28 bsc d 0.51 2 0 1 0 0 n l1 l2 e1 l e e 15 0 5 8 0.76 5.28 bsc 8.00 bsc 1.36 ref 0.25 bsc 8 1.27 bsc 1.70 1.75 0.05 0.33 0.36 0.15 0.19 c1 c b1 b a2 a1 a 1.90 2.16 0.25 0.48 0.46 0.20 0.24 0-8 ref 2. dimensioning and tolerancing per asme y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gate burrs. end. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 mm per side. 1. all dimensions are in millimeters. notes: d and e1 dimensions are determined at datum h. flash, but inclusive of any mismatch between the top and bottom of exclusive of mold flash, tie bar burrs, gate burrs and interlead 4. the package top may be smaller than the package bottom. dimensions 5. datums a and b to be determined at datum h. 6. "n" is the maximum number of terminal positions for the specified 7. the dimensions apply to the flat section of the lead between 0.10 to maximum material condition. the dambar cannot be located on the 8. dimension "b" does not include dambar protrusion. allowable dambar lower radius of the lead foot. identifier must be located within the index area indicated. 9. this chamfer feature is optional. if it is not present, then a pin 1 10. lead coplanarity shall be within 0.10 mm as measured from the mold flash, protrusions or gate burrs shall not exceed 0.15 mm per d and e1 are determined at the outmost extremes of the plastic body 0.25 mm from the lead tip. protrusion shall be 0.10 mm total in excess of the "b" dimension at the plastic body. package length. seating plane. dimensions symbol min. nom. max. - - - - - - - - - - kota besy 18-jul-16 18-jul-16 ** 12 to fit soc008 002-15548 package outline, 8 lead soic 5.28x5.28x2.16 mm soc008 document number: 001-98282 rev. *i page 39 of 142 S25FL127S 6.2 soic 16-lead package 6.2.1 soic 16 connection diagram figure 36. 16-lead soic package, top view 1 2 3 4 16 15 14 13 hold#/io3/reset# vcc reset# dnu nc nc si/io0 sck 5 6 7 8 12 11 10 9 wp#/io2 vss dnu dnu dnu rfu cs# so/io1 document number: 001-98282 rev. *i page 40 of 142 S25FL127S 6.2.2 soic 16 physical diagram figure 37. s03016 ? 16-lead wide plastic small outline package (300-mil body width) sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date 0.33 c 0.25 m d ca-b 0.20 c a-b 0.10 c 0.10 c 0.10 c d 2x 2. dimensioning and tolerancing per asme y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gate burrs. end. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 mm per side. 1. all dimensions are in millimeters. notes: d and e1 dimensions are determined at datum h. flash, but inclusive of any mismatch between the top and bottom of exclusive of mold flash, tie bar burrs, gate burrs and interlead 4. the package top may be smaller than the package bottom. dimensions 5. datums a and b to be determined at datum h. 6. "n" is the maximum number of terminal positions for the specified 7. the dimensions apply to the flat section of the lead between 0.10 to maximum material condition. the dambar cannot be located on the 8. dimension "b" does not include dambar protrusion. allowable dambar lower radius of the lead foot. identifier must be located within the index area indicated. 9. this chamfer feature is optional. if it is not present, then a pin 1 10. lead coplanarity shall be within 0.10 mm as measured from the h 0 d l2 n e a1 b c e e1 a 0.75 10.30 bsc 1.27 bsc 0.30 10.30 bsc 0.33 0 0.25 16 0.20 7.50 bsc 0.10 0.31 8 0.51 2.65 2.35 a2 2.05 2.55 b1 0.27 0.48 0.30 0.20 c1 l1 0.40 l 1.27 1.40 ref 0.25 bsc 0 5 15 0 0 1 2 - dimensions symbol min. nom. max. - - - - - - - - - - - - mold flash, protrusions or gate burrs shall not exceed 0.15 mm per d and e1 are determined at the outmost extremes of the plastic body 0.25 mm from the lead tip. protrusion shall be 0.10 mm total in excess of the "b" dimension at the plastic body. package length. seating plane. so3016 kota besy 24-oct-16 24-oct-16 *a 002-15547 package outline, 16 lead soic 12 to fit 10.30x7.50x2.65 mm so3016/sl3016/ss3016 sl3016 ss3016 document number: 001-98282 rev. *i page 41 of 142 S25FL127S 6.3 wson 6 x 5 package 6.3.1 wson 6 x 5 mm connection diagram figure 38. 8-contact wson 6 x 5 mm, top view notes: 1. lead 7 hold# / io3 or io3 / reset# function depends on the selected configuration, if the io3 / reset# function is used, the host system should actively or passively pull-up the io3 / reset# connection when quad mode is not enabled, or when cs# is high and a reset operation is not i ntended. 2. there is an exposed central pad on the und erside of the wson package. this pad sh ould not be connected to any voltage or sign al line on the pcb. connecting the central pad to gnd (v ss ) is possible, provided pcb routing ensures 0 mv difference between voltage at the wson gnd (v ss ) lead and the central exposed pad. 1 2 3 4 5 6 7 8 cs# so/io1 hold#/io3 or io3/reset # sck si/io0 wson wp#/io2 vcc vss document number: 001-98282 rev. *i page 42 of 142 S25FL127S 6.3.2 wson physical diagram figure 39. wnd008 ? wson 8-contact (6 x 5 mm) no-lead package sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date a maximum 0.15mm pull back (l1) may be present. bilateral coplanarity zone applies to the exposed heat sink pin #1 id on top will be located within the indicated zone. maximum allowable burr is 0. 076mm in all directions. dimension "b" applies to metallized terminal and is measured n is the total number of terminals. all dimensions are in millimeters. dimensioning and tolerancing conforms to asme y14.5m-1994. notes: max. package warpage is 0.05mm. 8 7. 6. 5 2. 4 3. 1. 9 10 the optional radius on the other end of the terminal, the dimension "b" should not be measured in that radius area. nd refers to the number of terminals on d side. 8 4 1.27 bsc. 0.40 6.00 bsc 5.00 bsc 4.00 3.40 0.20 min. 0.75 0.02 0.60 a1 k a e2 d e d2 b l nd n e 0.00 3.30 0.70 3.90 0.35 0.55 3.50 0.05 0.80 4.10 0.45 0.65 a3 0.20 ref dimensions symbol min. nom. max. between 0.15 and 0.30mm from terminal tip. if the terminal has slug as well as the terminals. kota lksu 13-feb-17 13-feb-17 ** 12 to fit wnd008 002-18755 package outline, 8 lead dfn 5.0x6.0x0.8 mm wnd008 4.0x3.4 mm epad (sawn) document number: 001-98282 rev. *i page 43 of 142 S25FL127S 6.4 fab024 24-ball bga package 6.4.1 connection diagram figure 40. 24-ball bga, 5 x 5 ball footprint (fab024), top view note: signal connections are in the same relative positions as fac024 bga, allowing a sing le pcb footprint to use either package. 3 25 4 1 nc nc nc reset#/ rfu b d e a c vss sck nc vcc dnu rfu cs# nc wp#/io2 dnu si/io0 so/io1 nc hold#/io3 dnu nc nc nc rfu nc document number: 001-98282 rev. *i page 44 of 142 S25FL127S 6.4.2 physical diagram figure 41. fab024 ? 24-ball ball grid array (8 x 6 mm) package sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date metallized mark indentation or other means. a1 corner to be identified by chamfer, laser or ink mark, n is the number of populated solder ball positions for matrix size md x me. when there is an even number of solder balls in the outer row, "sd" = ed/2 and when there is an odd number of solder balls in the outer row, "sd" or "se" = 0. position of the center solder ball in the outer row. "sd" and "se" are measured with respect to datums a and b and define the symbol "me" is the ball matrix size in the "e" direction. symbol "md" is the ball matrix size in the "d" direction. e represents the solder ball grid pitch. dimension "b" is measured at the maximum ball diameter in a plane ball position designation per jep95, section 3, spp-020. dimensioning and tolerancing methods per asme y14.5m-1994. "+" indicates the theoretical center of depopulated balls. 8. 9. 7 all dimensions are in millimeters. parallel to datum c. 5. 6 4. 3. 2. 1. notes: sd b ed ee me n 0.35 0.00 bsc 1.00 bsc 1.00 bsc 0.40 24 5 0.45 d1 md e1 e d a a1 0.20 - 4.00 bsc 4.00 bsc 5 6.00 bsc 8.00 bsc - - 1.20 - se 0.00 bsc dimensions symbol min. nom. max. "se" = ee/2. fab024 kota besy 18-jul-16 18-jul-16 ** 002-15534 package outline, 24 ball fbga 12 to fit 8.0x6.0x1.2 mm fab024 document number: 001-98282 rev. *i page 45 of 142 S25FL127S 6.5 fac024 24-ball bga package 6.5.1 connection diagram figure 42. 24-ball bga, 4 x 6 ball footprint (fac024), top view note: signal connections are in the same relati ve positions as fab024 bga, allowing a si ngle pcb footprint to use either package. 3 24 1 nc nc reset#/ rfu b d e a c vss sck vcc dnu rfu cs# wp#/io2 dnu si/io0 so/io1 hold#/io3 dnu nc nc rfu nc nc nc nc nc nc f document number: 001-98282 rev. *i page 46 of 142 S25FL127S 6.5.2 physical diagram figure 43. fac024 ? 24-ball ball grid array (6 x 8 mm) package 6.5.3 special handl ing instructions for fbga packages flash memory devices in bga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150c for prolonged periods of time. sheet of rev spec no. this drawing contains information which is the proprietary property of cypress semiconductor corporation. this drawing is received in confidence and its contents may not be disclosed without written consent of cypress semiconductor corporation. cypress title scale : company confidential package code(s) drawn by approved by date date metallized mark indentation or other means. a1 corner to be identified by chamfer, laser or ink mark, n is the number of populated solder ball positions for matrix size md x me. when there is an even number of solder balls in the outer row, "sd" = ed/2 and when there is an odd number of solder balls in the outer row, "sd" or "se" = 0. position of the center solder ball in the outer row. "sd" and "se" are measured with respect to datums a and b and define the symbol "me" is the ball matrix size in the "e" direction. symbol "md" is the ball matrix size in the "d" direction. e represents the solder ball grid pitch. dimension "b" is measured at the maximum ball diameter in a plane ball position designation per jep95, section 3, spp-020. dimensioning and tolerancing methods per asme y14.5m-1994. "+" indicates the theoretical center of depopulated balls. 8. 9. 7 all dimensions are in millimeters. parallel to datum c. 5. 6 4. 3. 2. 1. notes: sd b ed ee me n 0.35 0.50 bsc 1.00 bsc 1.00 bsc 0.40 24 4 0.45 d1 md e1 e d a a1 0.25 - 5.00 bsc 3.00 bsc 6 6.00 bsc 8.00 bsc - - 1.20 - se 0.50 bsc dimensions symbol min. nom. max. "se" = ee/2. fac024 kota besy 18-jul-16 18-jul-16 ** 002-15535 package outline, 24 ball fbga 12 to fit 8.0x6.0x1.2 mm fac024 document number: 001-98282 rev. *i page 47 of 142 S25FL127S software interface this section discusses the features and behav iors most relevant to host system softw are that interacts with the S25FL127S memor y device. 7. address space maps 7.1 overview 7.1.1 extended address the fl-s family of devices supports 32-bit addresses to enable higher density devices than allowed by previous generation (legacy) spi devices that supported only 24-bit addresses. a 24-bit byte resolution address can access only 16 mbytes (128 mbit s) of maximum density. a 32-bit byte resolution address allows direct addressing of up to a 4 gbytes (32 gbits) of address space. legacy commands continue to support 24-bit addresses for backwa rd software compatibility. extended 32-bit addresses are enabled in three ways: ? bank address register ? a software (command) loadable internal register that supplies the hi gh order bits of address when legacy 24-bit addresses are in use. ? extended address mode ? a bank address register bit that ch anges all legacy commands to expect 32 bits of address supplied from the host system. ? new commands ? that perform both legacy and new functions, which expect 32-bit address. the default condition at power-up or reset, is the bank addre ss register loaded with zeros and the extended address mode set fo r 24-bit addresses. this enables legacy software compat ible access to the first 128 mbits of a device. the S25FL127S, 128 mb density member of the fl-s family, s upports the extended address featur es in the same way but in essence ignores bits 31 to 24 of any address because the main fl ash array only needs 24 bits of address. this enables simple migration from the 128-mb density to higher density device s without changing the address handling aspects of software. 7.1.2 multiple address spaces many commands operate on the main flash memory array. some commands operate on address spaces separate from the main flash array. each separate address space uses the full 32-bit address but may only define a smal l portion of the available addr ess space. 7.2 flash memory array the main flash array is divided into erase units called sectors. the sectors are organized either as a hybrid combination of 4- kb and 64-kb sectors, or as uniform 256-kbyte se ctors. the sector organizatio n depends on the d8h_o contro l bit configuration in the status register 2 (sr2[7]). table 15. S25FL127S sector and memory address map, bottom 4-kbyte sectors sector size (kbyte) sector count sector range address range (byte address) notes 4 16 sa00 00000000h-00000fffh sector starting address ? sector ending address : : sa15 0000f000h-0000ffffh 64 255 sa16 00010000h-0001ffffh : : sa270 00ff0000h-00ffffffh document number: 001-98282 rev. *i page 48 of 142 S25FL127S note : these are condensed tables that use a coup le of sectors as references. there are add ress ranges that are not explicitly liste d. all 4-kb sectors have the pattern xxxx000h-xxxxfffh. all 64 -kb sectors have the pattern xxx0000h-xxxffffh. all 256-kb sectors have the pattern xx00000h-xx3ffffh, xx40000h-x x7ffffh, xx80000h-xxcffffh, or xxd0000h-xxfffffh. 7.3 id-cfi address space the rdid command (9fh) reads information from a separate flas h memory address space for dev ice identification (id) and common flash interface (cfi) information. see device id and common flash interface (id-cfi) address map on page 118 for the tables defining the contents of t he id-cfi address space. the id-cfi address spac e is programmed by cypress and read-only for the host system. 7.4 jedec jesd216b serial flash disc overable parameters (sfdp) space the rsfdp command (5ah) reads information from a separate flash memory address space for device identification, feature, and configuration information, in accord with the jedec jesd216b standard for serial flash discoverable parameters. the id-cfi address space is incorporated as one of the sfdp parameters. see section 12. serial flash discoverable parameters (sfdp) address map on page 115 for the tables defining the contents of the sf dp address space. the sfdp address space is programmed by cypress and re ad-only for the host system. table 16. S25FL127S sector and memory address map, top 4-kbyte sectors sector size (kbyte) sector count sector range address range (byte address) notes 64 255 sa00 0000000h-000ffffh sector starting address ? sector ending address : : sa255 00fe0000h-00feffffh 4 16 sa256 00ff0000h-00ff0fffh : : sa270 00fff000h-00ffffffh table 17. S25FL127S sector and memory address map, uniform 256-kbyte sectors sector size (kbyte) sector count sector range address range (byte address) notes 256 64 sa00 0000000h-003ffffh sector starting address ? sector ending address : : sa63 0fc0000h-0ffffffh document number: 001-98282 rev. *i page 49 of 142 S25FL127S 7.5 otp address space each fl-s family memory device has a 1024-byte one time prog ram (otp) address space that is separate from the main flash array. the otp area is divided into 32, individually lockable, 32-byte aligned and length regions. in the 32-byte region starting at address 0: ? the 16 lowest address bytes are programmed by cypress with a 128-bit random number. only cypress is able to program these bytes. ? the next 4 higher address bytes (otp lock bytes) are used to provide one bit per otp region to permanently protect each region from programming. the bytes are erased when shipped fr om cypress. after an otp region is programmed, it can be locked to prevent further programming, by programming the related protection bit in the otp lock bytes. ? the next higher 12 bytes of the lowest address region are re served for future use (rfu). the bits in these rfu bytes may be programmed by the host system but it must be understood that a future device may use t hose bits for protection of a larger otp space. the bytes are erased when shipped from cypress. the remaining regions are erased when shipped from cypress, a nd are available for programming of additional permanent data. refer to figure 44, otp address space on page 49 for a pictorial representation of the otp memory space. the otp memory space is intende d for increased system security. otp values, su ch as the random number programmed by cypress, can be used to ?mate? a flash component with t he system cpu/asic to prev ent device substitution. the configuration register freeze (cr1[0]) bit protects the entire otp memory space fr om programming when set to 1. this allows trusted boot code to control programming of otp regions then set the freeze bit to prevent further otp memory space programming during the remainder of normal power-on system operation. figure 44. otp address space . . . reserved lock bytes lock bits 31 to 0 ... when programmed to ?0? each lock bit protects its related 32 byte region from any further programming contents of region 0 { byte 0h byte 10h byte 1fh 32-byte otp region 31 32-byte otp region 30 32-byte otp region 29 32-byte otp region 3 32-byte otp region 2 32-byte otp region 1 32-byte otp region 0 16-byte random number document number: 001-98282 rev. *i page 50 of 142 S25FL127S 7.6 registers registers are small groups of memory cells used to configure how th e s25fl-s memory device operates or to report the status of device operations. the registers are access ed by specific commands. the commands (and hexadecimal instruct ion codes) used for each register are noted in each register description. the individual register bits may be volatile, non-volatile, or one time programmable (otp). the type for each bit is noted in each re gister description. the default state shown for each bit refers to the state after power-on reset, hardware reset, or software reset if the bit is volatile . if the bit is non-volatile or otp, the de fault state is the value of the bit when the device is shipped from cypress. non-volatile bits have the same cycling (erase and program) endurance as the main flash array. table 18. otp address map region byte address range (hex) contents initial delivery state (hex) region 0 000 least significant byte of cypress programmed random number cypress programmed random number ... ... 00f most significant byte of cypress programmed random number 010 to 013 region locking bits byte 10 [bit 0] locks region 0 from programming when = 0 ... byte 13 [bit 7] locks region 31 from programming when = 0 all bytes = ff 014 to 01f reserved for future use (rfu) all bytes = ff region 1 020 to 03f available for user programming all bytes = ff region 2 040 to 05f available for user programming all bytes = ff ... ... available for user programming all bytes = ff region 31 3e0 to 3ff available for user programming all bytes = ff table 19. register descriptions register abbreviation type bit location status register 1 sr1[7:0] volatile 7:0 configuration register 1 cr1[7:0] volatile 7:0 status register 2 sr2[7:0] rfu 7:0 autoboot register abrd[31:0] non-volatile 31:0 bank address register brac[7:0] volatile 7:0 ecc status register e ccsr[7:0] volatile 7:0 asp register aspr[15:1] otp 15:1 asp register aspr[0] rfu 0 password register pass[63:0 ] non-volatile otp 63:0 ppb lock register ppbl[7:1] volatile 7:1 ppb lock register ppbl[0] volatile read only 0 document number: 001-98282 rev. *i page 51 of 142 S25FL127S 7.6.1 status register 1 (sr1) related commands: read status register (rdsr1 05h), write registers (wrr 01h) , write enable (wren 06h), write disable (wrdi 04h), clear status register (clsr 30h). the status register contains both status and control bits: status register write disable (srwd) sr1[7] : places the device in the hardware protected mode when this bit is set to 1 and the wp# input is driven low. in this mode, the write registers (wrr) command is no longer accepted for execution, effectively locki ng the state of the srwd bit, bp bits, and conf iguration register bits by making the st atus register and configuration register read-only. if wp# is high the srwd bit and bp bits may be cha nged by the wrr command. if srwd is 0, wp# has no effect and the srwd bit and bp bits may be changed by the wrr command. the srwd bit has the same non-volatile endurance as the main flash array. program error (p_err) sr1[6] : the program error bit is used as a program o peration success or failure indication. when the program error bit is set to a 1, it indicates that there was an error in the last program operation. this bit will also be set when the user attempts to program within a protected main memory sector or lo cked otp region. when the program error bit is set to a 1, this bit can be reset to 0 with the clear status regi ster (clsr) command. this is a read-only bit and is not affected by the wrr command . ppb access register ppbar[7:0] non-volatile 7:0 dyb access register dybar[7:0] volatile 7:0 spi ddr data learning registers nvdlr[7:0] non-volatile 7:0 spi ddr data learning registers vdlr[7:0] volatile 7:0 table 20. status register 1 (sr1) bits field name function type default state description 7 srwd status register write disable non-volatile 0 1 = locks state of srwd, bp, and configuration register bits when wp# is low by ignoring wrr command 0 = no protection, even when wp# is low 6 p_err programming error occurred volatile, read only 0 1 = error occurred. 0 = no error 5 e_err erase error occurred volatile, read only 0 1 = error occurred 0 = no error 4 bp2 block protection volatile if cr1[3]=1, non-volatile if cr1[3]=0 1 if cr1[3]=1, 0 when shipped from cypress protects selected range of sectors (block) from program or erase 3 bp1 2 bp0 1 wel write enable latch volatile 0 1 = device accepts write registers (wrr), program or erase commands 0 = device ignore s write registers (wrr), program or erase commands this bit is not affected by wrr, only wren and wrdi commands affect this bit 0 wip write in progress volatile, read only 0 1 = device busy, a write registers (wrr), program, erase or other operation is in progress 0 = ready device is in standby mode and can accept commands table 19. register descriptions (continued) register abbreviation type bit location document number: 001-98282 rev. *i page 52 of 142 S25FL127S erase error (e_err) sr1[5] : the erase error bit is used as an erase operation su ccess or failure indication. when the erase error bit is set to a 1, it indicates that there was an error in th e last erase operation. this bit will also be set when the user at tempts to erase an individual protected main memory se ctor. the bulk erase command will not set e_err if a protected sector is found duri ng the command execution. when the erase error bi t is set to a 1, this bit can be reset to 0 with the clear status register (clsr) command. this is a read-only bit and is not affected by the wrr command. block protection (bp2, bp1, bp0) sr1[4:2] : these bits define the main flash array ar ea to be software-prot ected against program and erase commands. the bp bits are either volatile or non-vola tile, depending on the state of the bp non-volatile bit (bpnv) i n the configuration register. when one or more of the bp bits is set to 1, the relevant memory area is protected against program and erase. the bulk erase (be) command can be executed only when the bp bits are cleared to 0?s. see block protection on page 60 for a description of how the bp bit values select the memory array area protected. the bp bi ts have the same non-volatile endurance as the main flash array. write enable latch (wel) sr1[1] : the wel bit must be set to 1 to enable progra m, write, or erase operations as a means to provide protection against inadvertent changes to memory or register values. the writ e enable (wren) command execution sets the write enable latch to a 1 to allow any program, erase, or write commands to execute afte rwards. the write disable (wrdi) command can be used to set the write enable latch to a 0 to prevent all program, eras e, and write commands from execution. the wel bit is cleared to 0 at the end of any successful program, write, or erase operation. fo llowing a failed operation the wel b it may remain set and should be cleared with a wrdi command following a clsr command. after a power down/power up sequence, hardware reset, or software reset, the write enable latch is set to a 0 the wrr command does not affect this bit. write in progress (wip) sr1[0] : indicates whether the device is performing a program, write, erase operation, or any other operation, during which a new operation command will be ignored. when the bit is set to a 1 the device is busy performing an operation. while wip is 1, only read stat us (rdsr1 or rdsr2), erase suspend (er sp), program suspend (p gsp), clear status register (clsr), and software reset (reset) commands may be accepted. ersp and pgsp will only be a ccepted if memory array erase or program operations are in progress. the status r egister e_err and p_err bits are updated while wip = 1. when p_err or e_err bits are set to one, the wip bit will remain set t o1 indicating the device remains busy and unable to receive ne w operation commands. a clear status register (clsr) command must be received to retu rn the device to standby mode. when the wip bit is cleared to 0 no operation is in progress. this is a read-only bit. 7.6.2 configuration register 1 (cr1) related commands: read configuration regi ster (rdcr 35h), write registers (wrr 01h). t he configuration register bits can be changed using the wrr command with si xteen input cycles. the configuration register co ntrols certain interface and data protection functions. table 21. configuration register (cr1) bits field name function type default state description 7 lc1 latency code non-volatile 0 selects number of init ial read latency cycles see latency code tables 6 lc0 0 5 tbprot configures start of block protection otp 0 1 = bp starts at bottom (low address) 0 = bp starts at top (high address) 4 rfu rfu otp 0 reserved for future use 3 bpnv configures bp2-0 in status register otp 0 1 = volatile 0 = non-volatile 2 tbparm configures parameter sectors location otp 0 1 = 4-kb physical sectors at top, (high address) 0 = 4-kb physical sectors at bottom (low address) rfu in uniform sector devices 1 quad puts the device into quad i/o operation non-volatile 0 1 = quad 0 = dual or serial 0 freeze lock current state of bp2-0 bits in status register, tbprot and tbparm in configuration register, and otp regions volatile 0 1 = block protection and otp locked 0 = block protection and otp un-locked document number: 001-98282 rev. *i page 53 of 142 S25FL127S latency code (lc) cr1[7:6]: the latency code selects the number of mode and dummy cycles between the end of address and the start of read data outp ut for all read commands. some read commands send mode bits following the address to indi cate that the next command will be of the same type with an implied, rather than an explicit, instruct ion. the next command thus does not provide an instruction byte, only a new address a nd mode bits. this reduces the time needed to send each comma nd when the same command type is repeated in a sequence of commands. dummy cycles provide additional latency that is needed to complete the initial read access of the flash array before data can b e returned to the host system. so me read commands require addit ional latency cycles as the sck frequency is increased. the following latency code tables provide different latency settings that are configured by cypress. where mode or latency (dummy) cycles are shown in the tables as a dash, that read command is not supported at the frequency shown. read is supported only up to 50 mhz but the same late ncy value is assigned in each latency code and the command may be used when the device is operated at 50 mhz with any latency code setting. simila rly, only the fast read command is supported up to 108 mhz but the same 10b latency code is used for fast read up to 108 mhz and for the other dual and quad read commands up to 108 mhz. it is not necessary to change the latency co de from a higher to a lower frequency when operating at lower frequencies where a particular command is s upported. the latency code values for a higher frequency can be used for accesses at lower frequencies. top or bottom protection (tbprot) cr1[5]: this bit defines the operation of the blo ck protection bits bp2, bp1, and bp0 in the status register. as described in the status register section, the bp2-0 bits allow t he user to optionally protect a portion of the array, ranging from 1/64, 1/4, 1/2, etc., up to t he entire array. when tbprot is set to a 0 the block protection is defined to start f rom the top (maximum address) of the array. when tbpr ot is set to a 1 the block protection is defined to start from the bottom (zero address) of the array. the tbprot bit is otp and set to a 0 when shipped from cypress. if t bprot is programmed to 1, an attempt to change it back to 0 will fail and se t the program error bit (p_err in sr1[6]). the desired state of tbpr ot must be selected during the init ial configuration of the device during system manufa cture; before t he first program or erase operation on the main flash array. tbprot must not be programmed after programming or erasing is done in the main flash array. cr1[4]: reserved for future use block protection non-volatile (bpnv) cr1[3] : the bpnv bit defines whether or not the bp2-0 bits in the status register are volatile or non-volatile. the bpnv bit is otp and cleared to a 0 with the bp bits cleared to 000 when shipped from cypress. whe n bpnv is set to a 0 the bp2-0 bits in the st atus register are non-volatile . the time required to write the bp bits when they are non-volatile is t w . when bpnv is set to a 1 the bp2-0 bits in the status register are volatile and will be reset to binary 111 after por, hardware reset, or command reset. this allows the bp bits to be wr itten an unlimited number of times because they are volatile and the time to write the vo latile bp bits is the much faster t cs volatile register write time. if bpnv is programmed to 1, an attempt to change it back to 0 will fail and se t the program error bit (p_err in sr1[6]). tbparm cr1[2] : tbparm defines the logical location of the parameter blo ck. the parameter block consists of sixteen 4-kb small sectors, which replace one 64-kb sector. when tbparm is set to a 1 the parameter block is in the top of the memory array addres s space. when tbparm is set to a 0 the paramet er block is at the bottom of the array. tbparm is otp and set to a 0 when it ships from cypress. if tbparm is programmed to 1, an attempt to chang e it back to 0 will fail and set the program error bit (p_err in sr1[6]). table 22. latency codes freq. (mhz) lc read fast read read dual out read quad out dual i/o read quad i/o read (03h, 13h) (0bh, 0ch) (3bh, 3ch) (6bh, 6ch) (bbh, bch) (ebh, ech) mode dummy mode dummy mode dummy mode dummy mode dummy mode dummy 5011000000004021 8000- - 0808084424 9001- - 0808084124 10410- - 0808084225 10810--08-------- document number: 001-98282 rev. *i page 54 of 142 S25FL127S the desired state of tbparm must be selected during the initial configuration of the device during system manufacture; before t he first program or erase operation on the main flash array. tbparm must not be programmed after programming or erasing is done in the main flash array. tbprot can be set or cleared independent of the tbparm bit. theref ore, the user can elect to store parameter information from the bottom of the array and protec t boot code starting at the top of the array, and vice versa. or the user can select to store and protect the parameter information starti ng from the top or bottom together. when the memory array is logically configured as uniform 256-kb sectors, the tbparm bit is reserved for future use (rfu) and has no effect because all sectors are uniform size. quad data width (quad) cr1[1] : when set to 1, this bit switches the data widt h of the device to 4-bit quad mode. that is, wp# becomes io2 and hold# becomes io3. the wp# and hold# inputs are not monitored for their normal functions and are internally set to high (inactive). the commands for serial, dual output, and dual i/o read still function normally but, there is no need t o drive wp# and hold# inputs for those commands when switching be tween commands using different data path widths. the quad bit must be set to 1 when using read quad out, quad i/o read, and quad page program commands. the quad bit is non-volatile. freeze protection (freeze) cr1[0] : the freeze bit, when set to 1, locks the current state of the bp2-0 bits in status register, the tbprot and tbparm bits in the configuration register, and the otp address space. this preven ts writing, programming, or erasing these areas. as long as the freeze bit remains cleared to logic 0 the other bits of t he configuration register, includi ng freeze, are writable, and the otp address space is programmable. once the freeze bit has been written to a logic 1 it can only be cleared to a logic 0 by a power-off to power-on cycle or a ha rdware reset. software reset will not affect the state of the f reeze bit. the freeze bit is volatile and the def ault state of freeze after power-on is 0. the freeze bit can be set in parallel with updating other values in cr1 by a single wrr command. 7.6.3 status register 2 (sr2) related commands: read status register 2 (rdsr2 07h), write r egisters (wrr 01h). the status register 2 otp bits can be changed using the wrr co mmand with 24 input cycles. d8h sr2[7] : this bit controls the area erased by t he d8h instruction. the d8h instruction can be used to erase 64-kb or 256-kb size and aligned blocks. the option to erase 256- kb blocks in the lower density family memb ers allows for consistent software behavi or across all densities that can ease migrati on between different densities. when the default 64-kb erase option is in use the fla sh memory array has a hybrid of sixteen 4-kb sectors at the top or bottom of the array with all other sectors being 64 kb. individ ual 4-kb sectors are erased by the 20h inst ruction. a 64-kb block of 4-kb sectors or an indi vidual 64-kb sector can be erased by the d8h instruction. when the 25 6-kb option is in use, the flash memory array is treated as uniform 256-kb bl ocks that are individually erased by the d8h instruction. the desired state of this bit (d8h_o) must be selected during the initial conf iguration of the device during system manufacture - before the first program or erase operation on the main flas h array is performed. d8h_o must not be programmed after programming or erasing is done in the main flash array. table 23. status register 2 (sr2) bits field name function type default state description 7 d8h_o block erase size otp 0 1 = 256 kb erase (uniform sectors). 0 = 64 kb erase (hybrid 4-kb / 64-kb sectors). 6 02h_o page buffer wrap otp 0 1 = wrap at 512b 0 = wrap at 256b. 5 io3r_o io3 reset otp 0 1 = io3 alternate function is reset#. 0 = io3 alternate function is hold#. 4 rfu reserved 0 reserved for future use. 3 rfu reserved 0 reserved for future use. 2 rfu reserved 0 reserved for future use. 1 es erase suspend volatile, read only 0 1 = in erase suspend mode. 0 = not in erase suspend mode. 0 ps program suspend volatile, read only 0 1 = in program suspend mode. 0 = not in program suspend mode. document number: 001-98282 rev. *i page 55 of 142 S25FL127S 02h sr2[6] : this bit controls the page programming buffer address wrap point. legacy spi devices generally have used a 256-byte page programming buffer and defined that if data is loaded into the buffer be yond the 255-byte location, the address at which additional bytes are loaded would be wrapped to address 0 of t he buffer. the fl-s family provides a 512-byte page programming buffer that can increase programming perfor mance. for legacy software compatibility, th is configuration bit provides the option to continue the wrapping behavior at the 25 6-byte boundary or to enable full use of the available 512-byte buffer by not wrapping the load address at the 256-byte boundary. io3 reset non-volatile sr2[5] : this bit controls the por, hardware reset, or soft ware reset state of the io3 signal behavior. most legacy spi devices do not have a hardware reset input signal due to the limited signal count and connections available in tradi tional spi device packages. the S25FL127S device provides the option to use the io3 signal as a hardware reset input when the io3 signal is not in use for transferring information between the ho st system and the memory. this otp io3 reset configuration bit enables the device to start immediately ( boot) with io3 enabled for alternate use as a reset# signal. when left in the default state, the io3 signal has an alternate use as hold#. erase suspend (es) sr2[1] : the erase suspend bit is used to determine when the device is in erase suspend mode. this is a status bit that cannot be wri tten. when erase suspend bit is set to 1, the devi ce is in erase suspend mode. when erase suspend bit is cleared to 0, the device is not in erase suspend mode. refer to section 9.6.4 erase suspend and resume commands (ersp 75h or errs 7ah) on page 99 for details about the erase suspend/resume commands. program suspend (ps) sr2[0] : the program suspend bit is used to determine when the device is in program suspend mode. this is a status bit that cannot be writte n. when program suspend bit is set to 1, the device is in program suspend mode. when the program suspend bit is cleared to 0, the device is not in program suspend mode. refer to section 9.5.4 program suspend (pgsp 85h) and resume (pgrs 8ah) on page 95 for details. 7.6.4 autoboot register related commands: autoboot read (abrd 14h) and autoboot write (abwr 15h). the autoboot register provides a means to au tomatically read boot code as part of the power on reset, hardwa re reset, or softwa re reset process. 7.6.5 bank address register related commands: bank register access (brac b9h), write register (wrr 01h), bank regi ster read (brrd 16h) and bank register write (brwr 17h). the bank address register supplies additional high order bits of the main flash array byte boundary address for legacy commands that supply only the low order 24 bits of address. the bank address is used as the hi gh bits of address (above a23) for all 3-b yte address commands when extadd=0. the bank address is not us ed when extadd = 1 and traditional 3-byte address commands are instead required to provide all four bytes of address. table 24. autoboot register bits field name function type default state description 31 to 9 absa autoboot start address non-volatile 000000h 512-byte boundary address for the start of boot code access 8 to 1 absd autoboot start delay non-volatile 00h number of initial delay cycles between cs# going low and the first bit of boot code being transferred 0 abe autoboot enable non-volatile 0 1 = autoboot is enabled 0 = autoboot is not enabled table 25. bank address register (bar) bits field name function type default state description 7 extadd extended address enable volatile 0b 1 = 4 byte (32 bits) addressing required from command. 0 = 3 byte (24 bits) addressing from command + bank address. 6 to 2 rfu reserved volatile 00000b reserved for future use. 1 ba25 bank address volatile 0 rfu. 0 ba24 bank address volatile 0 rfu. document number: 001-98282 rev. *i page 56 of 142 S25FL127S extended address (extadd) bar[7]: extadd controls the address field size for le gacy spi commands. by default (power up reset, hardware reset, a nd software reset), it is cleared to 0 for 3 bytes (2 4 bits) of address. when set to 1, the legacy comm ands will require 4 bytes (32 bits) for the address field. this is a volatile bit. 7.6.6 ecc status register (eccsr) related commands: ecc read (eccrd 18h). eccsr does not have user programmable non- volatile bits. all defined bits are volatile read only status. the default state of these bits are set by hardware. see section 9.5.1.1 auto matic ecc on page 93 . the status of ecc in each ecc unit is provided by the 8-bit ecc status register (eccsr). th e ecc register read command is written followed by an ecc unit address. the contents of the st atus register then indicates, for the selected ecc unit, whether there is an error in the ecc unit eight bit error correction code, the e cc unit of 16 bytes of data, or that ecc is disabled for that ecc unit. eccsr[2] = 1 indicates an error was corrected in the ecc. eccsr[ 1] = 1 indicates an error was corrected in the ecc unit data. eccsr[0] = 1 indicates the ecc is disabled. the default state of ?0? for all these bits indicates no failures and ecc is enable d. eccsr[7:3] are reserved. these have undefined high or low values that can change fr om one ecc status read to another. these bits should be treated as ?don?t care? an d ignored by any software reading status. 7.6.7 asp register (aspr) related commands: asp r ead (asprd 2bh) and asp program (aspp 2fh). the asp register is a 16-bit otp memory lo cation used to permanen tly configure the behavior of ad vanced sector protection (asp) features. note: 1. default value depends on ordering part number, see initial delivery state on page 137 . table 26. ecc status register (eccsr) bits field name function type default state description 7 to 3 rfu reserved 0 reserved for future use 2 eecc error in ecc volatile, read only 0 1 = single bit error found in the ecc unit eight bit error correction code 0 = no error. 1 eeccd error in ecc unit data volatile, read only 0 1 = single bit error corrected in ecc unit data. 0 = no error. 0 eccdi ecc disabled volatile, read only 0 1 = ecc is disabled in the selected ecc unit. 0 = ecc is enabled in the selected ecc unit. table 27. asp register (aspr) bits field name function type default state description 15 to 9 rfu reserved otp 1 reserved for future use. 8 rfu reserved otp (note 1) reserved for future use. 7 rfu reserved otp (note 1) reserved for future use. 6 rfu reserved otp 1 reserved for future use. 5 rfu reserved otp (note 1) reserved for future use. 4 rfu reserved otp (note 1) reserved for future use. 3 rfu reserved otp (note 1) reserved for future use. 2 pwdmlb password protection mode lock bit otp 1 0 = password protection mode permanently enabled. 1 = password protection mode not permanently enabled. 1 pstmlb persistent protection mode lock bit otp 1 0 = persistent protecti on mode permanently enabled. 1 = persistent protec tion mode not permanently enabled. 0 rfu reserved otp (note 1) reserved for future use. document number: 001-98282 rev. *i page 57 of 142 S25FL127S reserved for future use (rfu) aspr[15:3, 0] . password protection mode lock bit (pwdmlb) aspr[2]: when programmed to 0, the password protection mode is permanently selected. persistent protection mode lock bit (pst mlb) aspr[1]: when programmed to 0, the persistent protection mode is permanently selected. pwdmlb and pstmlb are mutually exclusive, only one may be programmed to 0. when the asp protection mode is selected by programming either aspr[2] or aspr[1], certain otp configuration bits are locked and permanently protected from furthe r programming. the bits protected are: ? sr2[7:5] ? aspr ? pass the otp configuration must be selected before selecting the asp protection mode. attempting to program the listed otp configuration bits when aspr[2 :1] is not = 11b will result in a programming error with p_e rr (sr1[6]) set to 1. the asp protection mode should be selected dur ing system configuration to ensure that a malicious program does not select an undesired protection mode at a later time. by locking all the protection configuration via the asp mode selection, later altera tion of the protection methods by malicious programs is prevented. 7.6.8 password register (pass) related commands: password read (passrd e7h) and password program (passp e8h). 7.6.9 ppb lock register (ppbl) related commands: ppb lock read (plbrd a7h, plbwr a6h). table 28. password register (pass) bits field name function type default state description 63 to 0 pwd hidden password otp ffffffff-ffffff ffh non-volatile otp storage of 64-bit password. the password is no longer readable after the password protection mode is selected by programming asp register bit 2 to 0. table 29. ppb lock register (ppbl) bits field name function type default state description 7 to 1 rfu reserved volatile 00h reserved for future use 0 ppblock protect ppb array volatile persistent protection mode = 1 password protection mode = 0 0 = ppb array protected until next power cycle or hardware reset 1 = ppb array may be programmed or erased. document number: 001-98282 rev. *i page 58 of 142 S25FL127S 7.6.10 ppb access register (ppbar) related commands: ppb read (ppbrd e2h), ppb program (ppbp e3), ppb erase (ppbe e4). 7.6.11 dyb access register (dybar) related commands: dyb read (dybrd e0h) and dyb program (dybwr e1h). table 30. ppb access register (ppbar) bits field name function type default state description 7 to 0 ppb read or program per sector ppb non-volatile ffh 00h = ppb for the sector addressed by the ppbrd or ppbp command is programmed to 0, protecting that sector from program or erase operations. ffh = ppb for the sector addressed by the ppbrd or ppbp command is erased to 1, not protecting that sector from program or erase operations. table 31. dyb access register (dybar) bits field name function type default state description 7 to 0 dyb read or write per sector dyb volatile ffh 00h = dyb for the sector addressed by the dybrd or dybp command is cleared to 0, protecting that sector from program or erase operations. ffh = dyb for the sector addr essed by the dybrd or dybp command is set to 1, not protecting that sector from program or erase operations. document number: 001-98282 rev. *i page 59 of 142 S25FL127S 8. data protection 8.1 secure silicon region (otp) the device has a 1024-byte one time program (otp) address space th at is separate from the main flash array. the otp area is divided into 32, individually lockable, 32-byte aligned and length regions. the otp memory space is intended for increased system security . otp values can ?mate? a flash component with the system cpu/asic to prevent device substitution. see otp address space on page 49 , one time program array commands on page 102 , and otp read (otpr 4bh) on page 102 . 8.1.1 reading otp memory space the otp read command uses the same protocol as fast read. otp read operations outside the valid 1-kb otp address range will yield indeterminate data. 8.1.2 programming otp memory space the protocol of the otp programming command is the same as page program. the otp program command can be issued multiple times to any given otp address, but this address space can never be erased. automatic ecc is programmed on the first programming operation to each 16-byte region. programming within a 16-byte region more than once disables the ecc. it is recommended to program each 16-byte portion of each 32-byte region once so that ecc remains enabled to provide the best data integrity. the valid address range for otp program is depicted in figure 44, otp address space on page 49 . otp program operations outside the valid otp address range will be ignored and the wel in sr1 will remain high (set to 1). otp program operations whil e freeze = 1 will fail with p_err in sr1 set to 1. 8.1.3 cypress programmed random number cypress standard practice is to program the low order 16 bytes of the otp memory space (locations 0x0 to 0xf) with a 128-bit random number using the linear congruential random number meth od. the seed value for the algorithm is a random number concatenated with the day and time of tester insertion. 8.1.4 lock bytes the lsb of each lock byte protects the lowest address region related to the byte, the msb protects the highest address region related to the byte. the next higher address byte similarly prot ects the next higher 8 regions. the lsb bit of the lowest addre ss lock byte protects the higher address 16 bytes of the lowest address region. in other word s, the lsb of location 0x10 protects all t he lock bytes and rfu bytes in the lowest address region from further programming. see section 7.5 otp address space on page 49 . 8.2 write enable command the write enable (wren) command must be written prior to an y command that modifies non-volatile data. the wren command sets the write enable latch (wel) bit. the wel bit is cleared to 0 (disables writes) during power-u p, hardware reset, or after the device completes t he following commands: ?reset ? page program (pp) ? sector erase (se) ? bulk erase (be) ? write disable (wrdi) ? write registers (wrr) ? quad-input page programming (qpp) ? otp byte programming (otpp) document number: 001-98282 rev. *i page 60 of 142 S25FL127S 8.3 block protection the block protect bits (status register bits bp2, bp1, bp0) in combination with the configurati on register tbprot bit can be us ed to protect an address range of the main flash array from program and erase operations. the size of the range is determined by t he value of the bp bits and the upper or lower starting point of the range is selected by the tbprot bit of the configuration regi ster. when block protection is enabled (i.e., any bp2-0 are set to 1), advanced sector protection (asp) can still be used to protect sectors not protected by the block protecti on scheme. in the case that both asp and bl ock protection are used on the same secto r the logical or of asp and block protection related to the sector is used. recommendation: asp an d block protection should not b e used concurrently. use one or the other, but not both. table 32. upper array start of protection (tbprot = 0) status register content protected fraction of memory array protected memory (kbytes) bp2 bp1 bp0 fl127s 128 mb 0 0 0 none 0 0 0 1 upper 64th 256 0 1 0 upper 32nd 512 0 1 1 upper 16th 1024 1 0 0 upper 8th 2048 1 0 1 upper 4th 4096 1 1 0 upper half 8192 1 1 1 all sectors 16384 table 33. lower array start of protection (tbprot = 1) status register content protected fraction of memory array protected memory (kbytes) bp2 bp1 bp0 fl127s 128 mb 0 0 0 none 0 0 0 1 lower 64th 256 0 1 0 lower 32nd 512 0 1 1 lower 16th 1024 1 0 0 lower 8th 2048 1 0 1 lower 4th 4096 1 1 0 lower half 8192 1 1 1 all sectors 16384 document number: 001-98282 rev. *i page 61 of 142 S25FL127S 8.3.1 freeze bit bit0 of the configuration register is the freeze bit. the freeze bit locks the bp2-0 bi ts in status register 1 and the tbprot b it in the configuration register to their value at the time the fr eeze bit is set to 1. once the freeze bit has been written to a logic 1 it cannot be cleared to a logic 0 until a power-on-reset is exec uted. as long as the freeze bit is cleared to logic 0 the statu s register bp bits and the tbprot bit of the configuration register are writ able. the freeze bit also protects the entire otp memory space from programming when set to 1. any attempt to change the bp bits with the wrr command while freeze = 1 is ignored and no error status is set. 8.3.2 write protect signal the write protect (wp#) input in combinati on with the status register write disable (srwd) bit provide hardware input signal controlled protection. when wp# is low and srwd is set to 1 the status and configuration register is protected from alteration. this prevents disabling or ch anging the protection defined by the block protect bits. see section 7.6.1 status register 1 (sr1) on page 51 8.4 advanced sector protection advanced sector protection (asp) is the name used for a set of independent hardware and softwar e methods used to disable or enable programming or erase operations, individually, in any or all sectors. an overview of these methods is shown in figure 45, advanced sector protection overview on page 61 . block protection and asp protection settings for each sector are logically or?d to def ine the protection for each sector, i.e. if either mechanism is protecting a sector the sector cannot be programmed or erased. refer to block protection on page 60 for full details of the bp2-0 bits. figure 45. advanced sector protection overview asp register one time programmable password method ( aspr[2]=0) persistent method ( aspr[1]=0) 64 - bit password (one time protect) pbb lock bit ?0? = ppbs locked memory array sector n - 2 sector n - 1 sector n 1.) n = highest address sector ppb 0 persistent protection bit (ppb) ppb n - 2 ppb 1 ppb 2 ppb n - 1 ppb n dyb 0 dynamic protection bit (dyb) dyb n - 2 dyb 1 dyb 2 dyb n - 1 dyb n 2.) 3.) dyb are volatile bits ?1?=ppbs unlocked 64 - (one time protect) sector 0 sector 1 sector 2 a sector is protected if its ppb =?0? or its dyb = ?0? ppb are programmed individually but erased as a group 4.) ppb lock bit is volatile and defaults to ?1? (persistent mode).or ?0? (password mode) upon reset 5.) ppb lock = ?0? locks all ppbs to their current state 6.) password method requires a password to set ppb lock to ?1? to enable program or erase of ppb bits 7.) persistent method only allows ppb lock to be cleared to ?0? to prevent program or erase of ppb bits. power off or hardware reset required to set ppb lock to ?1? document number: 001-98282 rev. *i page 62 of 142 S25FL127S every main flash array sector has a non-vo latile (ppb) and a vo latile (dyb) protection bit asso ciated with it. wh en either bit is 0, the sector is protected from pr ogram and erase operations. the ppb bits are protected from program and erase when the ppb lo ck bit is 0. there are two meth ods for managing the state of the ppb lock bit, persistent prot ection and password protection. the persistent protection method sets the ppb lock bit to 1 durin g por, or hardware reset so that the ppb bits are unprotected by a device reset. there is a command to clear the ppb lock bit to 0 to protect the ppb. there is no comman d in the persistent protection method to set the ppb lock bit to 1, therefore the ppb lock bit will rema in at 0 until the next power-off or hardwar e reset. the persistent protection method allows boot code the option of changing sector prot ection by programming or erasing the ppb, then protecting the ppb from furt her change for the remainder of normal system operation by clea ring the ppb lock bit to 0. thi s is sometimes called boot-code controlled sector protection. the password method clears the ppb lock bit to 0 during por, or hardwa re reset to protect the pp b. a 64 bit password may be permanently programmed and hidden for the password method. a comm and can be used to provide a password for comparison with the hidden password. if the passw ord matches, the ppb lock bit is set to 1 to u nprotect the ppb. a command can be used to clear the ppb lock bit to 0. this method requires use of a password to control ppb protection. the selection of the ppb lock bit management method is made by programming otp bits in the asp register so as to permanently select the method used. 8.4.1 asp register the asp register is used to permanently configure the behavior of advanced se ctor protection (asp) features. see table 27, asp register (aspr) on page 56 . as shipped from the factory, all devices default asp to the persistent protection mo de, with all sectors u nprotected, when powe r is applied. the device programmer or host system must then choose which sector protection method to use. programming either of the, one-time programmable, protecti on mode lock bits, locks the part pe rmanently in the selected mode: ? aspr[2:1] = 11 = no asp mode selected, pers istent protection mo de is the default. ? aspr[2:1] = 10 = persistent protec tion mode perm anently selected. ? aspr[2:1] = 01 = password protecti on mode permanently selected. ? aspr[2:1] = 00 = illegal condition, attempting to program both bits to 0 results in a programming failure. asp register programming rules: ? if the password mode is chosen, the password must be pr ogrammed prior to setting the protection mode lock bits. ? once the protection mode is selected, the protection mode lock bits are permanen tly protected from programming and no further changes to the asp register is allowed. the programming time of the asp register is the same as the ty pical page programming time. the system can determine the status of the asp register programming operation by re ading the wip bit in the status register. see status register 1 (sr1) on page 51 for information on wip. after selecting a sector protecti on method, each sector can operate in each of the following states: ? dynamically locked ? a sector is protected and can be changed by a simple command. ? persistently locked ? a sector is protected and cannot be changed if its ppb bit is 0. ? unlocked ? the sector is unprotected and can be changed by a simple command. the block protection bits may be used to lock a sector/sectors. document number: 001-98282 rev. *i page 63 of 142 S25FL127S 8.4.2 persistent protection bits the persistent protection bits (ppb) are located in a se parate nonvolatile flash array. one of the ppb bits is related to each sector. when a ppb is 0, its related se ctor is protected from program and erase operat ions. the ppb are programm ed individually but mus t be erased as a group, similar to the way individual words may be pr ogrammed in the main array but an entire sector must be eras ed at the same time. the ppb have the same program and erase e ndurance as the main flash memory array. preprogramming and verification prior to erasure are handled by the device. programming a ppb bit requ ires the typical page programming time. erasing all the ppbs requires typical sector erase time. duri ng ppb bit programming and ppb bit erasing, status is available by re ading the status register. read ing of a ppb bit requires the initial access time of the device. notes : ? each ppb is individually programmed to 0 and all are erased to 1 in parallel. ? if the ppb lock bit is 0, the ppb program or ppb erase command does not execute and fails wi thout programming or erasing the ppb. ? the state of the ppb for a given sector can be verified by using the ppb read command. 8.4.3 dynamic protection bits dynamic protection bits are volatile and unique for each sector and can be individually modified. dyb only control the protecti on for sectors that have their ppb set to 1. by issuing the dyb write command, a dyb is cleared to 0 or set to 1, thus placing each se ctor in the protected or unprotected state res pectively. this feature allows software to easily protect sectors against inadvertent changes, yet does not prevent the easy removal of protection when changes are needed. the dybs can be set or cleared as often as needed as they are volatile bits. 8.4.4 ppb lock bit (ppbl[0]) the ppb lock bit is a volatile bit for protecting all ppb bits. when cleared to 0, it locks all ppbs and when set to 1, it allo ws the ppbs to be changed. the plbwr command is used to clear the ppb lock bit to 0. the ppb lock bit must be clear ed to 0 only after all the ppbs are configured to the desired settings. in persistent protection mode, the ppb lock is set to 1 during por or a ha rdware reset. when cleared to 0, no software command sequence can set the ppb lock bit to 1, only another hardware reset or power-up can set the ppb lock bit. in the password protection mode, the ppb lock bit is cleare d to 0 during por or a hardware reset. the ppb lock bit can only be set to 1 by the password unlock command. 8.4.5 sector protection states summary each sector can be in one of the following protection states: ? unlocked ? the sector is unprotected and protection can be changed by a simple command. t he protection state defaults to unprotected after a power cycle, software reset, or hardware reset. the block protection bits may be used to protect a sector/sectors. ? dynamically locked ? a sector is protec ted and protection can be changed by a simp le command. the protection state is not saved across a power cycle or reset. ? persistently locked ? a sector is protected and protecti on can only be changed if the ppb lock bit is set to 1. the protection state is non-volatile and saved across a power cycle or reset. changing the protection state requires programming and or erase of the ppb bits document number: 001-98282 rev. *i page 64 of 142 S25FL127S 8.4.6 persistent protection mode the persistent protection method sets the ppb lock bit to 1 during por or hardware reset so that the ppb bits are unprotected. software reset does not affect the ppb lock bit. the plbwr command can clear the ppb lock bit to 0 to protect the ppb. there is no command to se t the ppb lock bit t herefore the ppb lock bit will remain at 0 unt il the next power-off or hardware reset. table 34. sector protection states protection bit values sector state ppb lock ppb dyb 1 1 1 unprotected ? ppb and dyb are changeable 1 1 0 protected ? ppb and dyb are changeable 1 0 1 protected ? ppb and dyb are changeable 1 0 0 protected ? ppb and dyb are changeable 0 1 1 unprotected ? ppb not changeable, dyb is changeable 0 1 0 protected ? ppb not changeable, dyb is changeable 0 0 1 protected ? ppb not changeable, dyb is changeable 0 0 0 protected ? ppb not changeable, dyb is changeable document number: 001-98282 rev. *i page 65 of 142 S25FL127S 8.4.7 password protection mode password protection mode allows an even higher level of security t han the persistent sector protec tion mode, by requiring a 64- bit password for unlocking the ppb lock bit. in addition to this password requirement, after power up and hardware reset, the ppb l ock bit is cleared to 0 to ensure protection at power-up. successf ul execution of the password un lock command by entering the entir e password sets the ppb lock bit to 1, allowing for sector ppb modifications. password protection notes: ? once the password is programmed and verified, the password mode (aspr[2]=0) must be set in order to prevent reading the password. ? the password program command is only capable of programmi ng ?0?s. programming a 1 after a cell is programmed as a 0 results in the cell left as a 0 with no programming error set. ? the password is all 1?s when shipped from cypress. it is located in its own memory space and is accessible through the use of the password program and password read commands. ? all 64-bit password combinations are valid as a password. ? the password mode, once programmed, prevents reading t he 64-bit password and further password programming. all further program and read commands to the password region ar e disabled and these commands are ignored. there is no means to verify what the password is after the password mode lock bit is selected. password ve rification is only allowed before selecting the password protection mode. ? the protection mode lock bits are not erasable. ? the exact password must be entered in order for the unlocki ng function to occur. if the password unlock command provided password does not match the hidden internal password, the unl ock operation fails in the same manner as a programming operation on a protected sector. the p_err bit is set to one, the wip bit remains set, and the ppb lock bit remains cleared to 0. ? the password unlock command cannot be ac cepted any faster than once every 100 s 20 s. this makes it take an unreasonably long time (58 million years) for a hacker to run thro ugh all the 64-bit combinations in an attempt to correctly match a password. the read status register 1 command may be used to read the wip bit to determine when the device has completed the password unlock command or is ready to a ccept a new command. when a valid password is provided the password unlock command does not insert the 100 s delay before returning the wip bit to 0. ? if the password is lost after selecting the passw ord mode, there is no way to set the ppb lock bit. ? ecc status may only be read from sector s that are readable. in read protection mode the addresses are forced to the boot sector address. ecc status is shown in that sector while read protection mode is active. document number: 001-98282 rev. *i page 66 of 142 S25FL127S 9. commands all communication between the host system and S25FL127S memo ry devices is in the form of units called commands. all commands begin with an instruction that selects the type of information transfer or device operation to be performed. comma nds may also have an address, instruction modifier, latency period, da ta transfer to the memory, or data transfer from the memory. all instruction, address, and data information is transferred serially between the host system and memory device. all instructions are transferred from host to memory as a single bit serial sequence on the si signal. single bit wide commands may provide an address or data sent only on the si signal. data may be sent back to the host serially on so signal. dual or quad output commands provide an address sent to the memo ry only on the si signal. data will be returned to the host as a sequence of bit pairs on io0 and io1 or four bit (nibble) groups on io0, io1, io2, and io3. dual or quad input/output (i/o) commands provide an address sent from the host as bit pairs on io0 and io1 or, four bit (nibble ) groups on io0, io1, io2, and io3. data is returned to the host similarly as bit pairs on io0 and io1 or, four bit (nibble) grou ps on io0, io1, io2, and io3. commands are structured as follows: ? each command begins with an eight bit (byte) instruction. ? the instruction may be stand alone or may be followed by addres s bits to select a location within one of several address spaces in the device. the address may be either a 24-bit or 32-bit address. ? the serial peripheral interface with multip le io provides the option for each transf er of address and data information to be done one, two, or four bits in parallel. this enables a trade off between the number of signal connections (io bus width) and the speed of information transfer. if th e host system can support a two or four bi t wide io bus the memory performance can be increased by using the instructions that provide parallel two bit (dual) or parallel four bit (quad) transfers. ? the width of all transfers following the instru ction are determined by the instruction sent. ? all single bits or parallel bit groups are transferred in most to least significant bit order. ? some instructions send instruction modifier (mode) bits followin g the address to indicate that the next command will be of the same type with an implied, rather than an explicit, instruction. the next comman d thus does not provide an instruction byte, only a new address and mode bits. this reduces the time needed to send each command when the same command type is repeated in a sequence of commands. ? the address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before read data is returned to the host. ? read latency may be zero to se veral sck cycles (also referred to as dummy cycles). ? all instruction, address, mode, and data information is transferr ed in byte granularity. addresses are shifted into the device with the most significant byte first. all data is transferred with the lowest address byte sent first. following bytes of data are sent in lowest to highest byte addre ss order i.e. the byte address increments. ? all attempts to read the flash memory array during a progr am, erase, or a write cycle (e mbedded operations) are ignored. the embedded operation will continue to exec ute without any affect. a very limited se t of commands are accepted during an embedded operation. these are discussed in the individual command descriptions. while a program, erase, or write operation is in progress, it is recommended to check that the write-in progress (wip) bit is 0 before issuing most commands to the device, to ensure the new command can be accepted. ? depending on the command, the time for execution varies. a command to read status information from an executing command is available to determine when the command co mpletes execution and whether the command was successful. ? although host software in some cases is used to directly co ntrol the spi interface signals, the hardware interfaces of the host system and the memory device generally handle the details of sig nal relationships a nd timing. for this reason, signal relationships and timing are not covered in detail within this software interface focused section of the document. instead, the focus is on the logical sequence of bits transferred in ea ch command rather than the signal timing and relationships. following are some general signal relationship descriptions to keep in mind. for additional information on the bit level format and signal timing relationships of commands, see command protocol on page 15 . document number: 001-98282 rev. *i page 67 of 142 S25FL127S ? the host always controls the chip select (cs#), serial clock (sck), and serial input (si) - si for single bit wide transfers. the memory drives serial output (so) for si ngle bit read transfers. the host and memory alternately drive the io0-io3 signals during dual and quad transfers. ? all commands begin with the host selecting the memory by driving cs# low before th e first rising edge of sck. cs# is kept low throughout a command and when cs# is returned high the command ends. generally, cs# remains low for eight bit transfer multiples to transfer byte granular ity information. some commands will not be accepted if cs# is returned high not at an 8 bit boundary. 9.1 command set summary 9.1.1 extended addressing to accommodate addressing above 128 mb, there are three options: 1. new instructions are provided with 4-byte add ress, used to access up to 32 gb of memory. 2. for backward compatibility to the 3-byte address instructions , the standard instructions can be used in conjunction with the extadd bit in the bank address regi ster (bar[7]). by default bar[7] is cleared to 0 (following power up and hardware reset), to enable 3-byte (24-bit) addressing. when set to 1, the legacy commands are changed to require 4 bytes (32 bits) for the address field. the following instructions can be used in conjunction with extadd bit to switch from 3 bytes to 4 bytes of address field. instruction name description code (hex) 4fast_read read fast (4-byte address) 0c 4read read (4-byte address) 13 4dor read dual out (4-byte address) 3c 4qor read quad out (4-byte address) 6c 4dior dual i/o read (4-byte address) bc 4qior quad i/o read (4-byte address) ec 4pp page program (4-byte address) 12 4qpp quad page program (4-byte address) 34 4p4e parameter 4-kb erase (4-byte address) 21 4se erase 64/256 kb (4-byte address) dc instruction name description code (hex) read read (3-byte address) 03 fast_read read fast (3-byte address) 0b dor read dual out (3-byte address) 3b qor read quad out (3-byte address) 6b dior dual i/o read (3-byte address) bb qior quad i/o read (3-byte address) eb pp page program (3-byte address) 02 qpp quad page program (3-byte address) 32 p4e parameter 4-kb erase (3-byte address) 20 se erase 64 / 256 kb (3-byte address) d8 document number: 001-98282 rev. *i page 68 of 142 S25FL127S 3. for backward compatibility to the 3-byte addressing, the sta ndard instructions can be used in conjunction with the bank address register: a. the bank address register is used to switch between 128-mbit (16-mbyte) banks of memory, the standard 3-byte address selects an address within the bank selected by the bank address register. i. the host system writes the bank address r egister to access beyond the first 128 mbits of memory. ii. this applies to read, er ase, and program commands. b. the bank register provides the high order (4th) byte of address, which is used to addr ess the available memory at addresses greater than 16 mbytes. c. bank register bits are volatile. i. on power up, the default is bank0 (the lowest address 16 mbytes). d. for read, the device will continuously trans fer out data until the end of the array. i. there is no bank to bank delay. ii. the bank address register is not updated. iii. the bank address register value is used only for the initial address of an access. 9.1.2 command summary sorted by function table 35. bank address map bank address register bits bank memory array address range (hex) bit 1 bit 0 0 0 0 00000000 00ffffff table 36. S25FL127S command set (sorted by function) function command name command description instruction value (hex) maximum frequency (mhz) read device identification read_id (rems) read electronic manufacturer signature 90 108 rdid read id (jedec manufacturer id and jedec cfi) 9f 108 rsfdp read jedec serial flash discoverable parameters 5a 108 res read electronic signature ab 50 document number: 001-98282 rev. *i page 69 of 142 S25FL127S register access rdsr1 read status register 1 05 108 rdsr2 read status register 2 07 108 rdcr read configuration register 1 35 108 wrr write register (status-1, configuration-1) 01 108 wrdi write disable 04 108 wren write enable 06 108 clsr clear status register 1 - erase/prog. fail reset 30 108 eccrd ecc read (4-byte address) 18 108 abrd autoboot register read 14 108 (quad=0) 108 (quad=1) abwr autoboot register write 15 108 brrd bank register read 16 108 brwr bank register write 17 108 brac bank register access (legacy command formerly used for deep power down) b9 108 dlprd data learning pattern read 41 108 pnvdlr program nv data learning register 43 108 wvdlr write volatile data learning register 4a 108 read flash array read read (3- or 4-byte address) 03 50 4read read (4-byte address) 13 50 fast_read fast read (3- or 4-byte address) 0b 108 4fast_read fast read (4-byte address) 0c 108 dor read dual out (3- or 4-byte address) 3b 108 4dor read dual out (4-byte address) 3c 108 qor read quad out (3- or 4-byte address) 6b 108 4qor read quad out (4-byte address) 6c 108 dior dual i/o read (3- or 4-byte address) bb 108 4dior dual i/o read (4-byte address) bc 108 qior quad i/o read (3- or 4-byte address) eb 108 4qior quad i/o read (4-byte address) ec 108 program flash array pp page program (3- or 4-byte address) 02 108 4pp page program (4-byte address) 12 108 qpp quad page program (3- or 4-byte address) 32 80 qpp quad page program - alternate inst ruction (3- or 4-byte address) 38 80 4qpp quad page program (4-byte address) 34 80 pgsp program suspend 85 108 pgrs program resume 8a 108 table 36. S25FL127S command set (sorted by functi on) (continued) function command name command description instruction value (hex) maximum frequency (mhz) document number: 001-98282 rev. *i page 70 of 142 S25FL127S erase flash array p4e parameter 4-kb, sector eras e (3- or 4-byte address) 20 108 4p4e parameter 4-kb, sector erase (4-byte address) 21 108 be bulk erase 60 108 be bulk erase (alternate command) c7 108 se erase 64 kb or 256 kb (3- or 4-byte address) d8 108 4se erase 64 kb or 256 kb (4-byte address) dc 108 ersp erase suspend 75 108 errs erase resume 7a 108 one time program array otpp otp program 42 108 otpr otp read 4b 108 advanced sector protection dybrd dyb read e0 108 dybwr dyb write e1 108 ppbrd ppb read e2 108 ppbp ppb program e3 108 ppbe ppb erase e4 108 asprd asp read 2b 108 aspp asp program 2f 108 plbrd ppb lock bit read a7 108 plbwr ppb lock bit write a6 108 passrd password read e7 108 passp password program e8 108 passu password unlock e9 108 reset reset software reset f0 108 mbr mode bit reset ff 108 rfu reserved-a3 reserved a3 108 rfu reserved-18 reserved 18 rfu reserved-e5 reserved e5 rfu reserved-e6 reserved e6 table 36. S25FL127S command set (sorted by functi on) (continued) function command name command description instruction value (hex) maximum frequency (mhz) document number: 001-98282 rev. *i page 71 of 142 S25FL127S 9.1.3 read device identification there are multiple commands to read information about the device manufacturer, device type, and device features. spi memories from different vendors have used different commands and formats for reading information about the memories. the fl-s family supports the three most common device information commands. 9.1.4 register read or write there are multiple registers for reporting embedded operation st atus or controlling device c onfiguration options. there are commands for reading or writing these registers. registers contai n both volatile and non-volatile bits. non-volatile bits in re gisters are automatically erased and programmed as a single (write) operation. 9.1.4.1 monitoring operation status the host system can determine when a write, pr ogram, erase, suspend or ot her embedded o peration is complete by monitoring the write in progress (wip) bit in the status register. the read from status register 1 command provides the state of the wip bit. the program error (p_err) and erase error (e_err) bits in the status register indicate whether the most recent program or erase command has not completed successfully. when p_err or e_err bits are set to one, the wip bit will remain set to 1 indicating th e device remains busy and unable to receive most new operation commands. only status read (rds r1 05h), status clear (clsr 30h), write disable (wrdi 04h), a nd software reset (reset 0fh) ar e valid commands when p_err or e_err is set to 1. a clear status register (clsr) followed by a write disable (wrdi) command must be sent to return the device to standby state. clsr clears the wip, p_err, and e_err bits. wrdi clears the wel bi t. alternatively, hardware rese t, or software reset (reset) may be used to return the device to standby state. 9.1.4.2 configuration there are commands to read, write, and prot ect registers that control interface path width, interface timing, interface address length, and some aspects of data protection. 9.1.5 read flash array data may be read from the memory starting at any byte boundary. data bytes are sequ entially read from incrementally higher byte addresses until the host ends the data transfer by driving cs# i nput high. if the byte address reaches the maximum address of t he memory array, the read will continue at address 0 of the array. there are several different read commands to specif y different access latency and data path widths. ? the read command provides a single address bit per sck rising edge on the si signal with read data returning a single bit per sck falling edge on the so signal. this command has zero latency between the address and the returning data but is limited to a maximum sck rate of 50 mhz. ? other read commands have a latency period between the ad dress and returning data but can operate at higher sck frequencies. the latency depends on the configuration register latency code. ? the fast read command provides a single address bit per sc k rising edge on the si signal with read data returning a single bit per sck falling edge on the so signal and may operate up to 108 mhz. ? dual or quad output read commands provide address a single bit per sck rising edge on the si / io0 signal with read data returning two bits, or four bits of data per sck falling edge on the io0-io3 signals. ? dual or quad i/o read commands provide address two bits or four bits per sck rising edge with read data returning two bits, or four bits of data per sck falling edge on the io0-io3 signals. 9.1.6 program flash array programming data requires two commands: write enable (wren) , and page program (pp or qpp). the page program command accepts from 1 byte up to 256 or 512 consecutive bytes of da ta (page) to be programmed in one operation. programming means that bits can either be left at 1, or programmed from 1 to 0. changing bits from 0 to 1 requires an erase operation. document number: 001-98282 rev. *i page 72 of 142 S25FL127S 9.1.7 erase flash array the sector erase (se) and bulk erase (be) commands set all the bits in a sector or the entire memory array to 1. a bit needs to be first erased to 1 before programming can change it to a 0. while bi ts can be individually programmed from a 1 to 0, erasing bit s from 0 to 1 must be done on a sector-wide (se) or array-wide (be) level. the write enable (wren) command must precede an erase command. 9.1.8 otp, block protection, an d advanced sector protection there are commands to read and program a separate one time pr ogrammable (otp) array for permanent data such as a serial number. there are commands to control a contiguous group (block) of flash memory array sectors th at are protected from program and erase operations. there are commands to control which individual flash memory a rray sectors are protected from program and erase operations. 9.1.9 reset there is a command to reset to the default conditions present af ter power on to the device. there is a command to reset (exit f rom) the enhanced performance read modes. 9.1.10 reserved some instructions are reserved for future use. in this generatio n of the fl-s family, some of these command instructions may be unused and not affect dev ice operation, some may have undefined results. some commands are reserved to ensure that a legacy or alternate source device command is allowed without affect. this allows legacy software to issue some commands that are not relevant for the current generation fl-s family with the assurance these commands do not cause some unexpected action. some commands are reserved for use in special versions of the fl -s not addressed by this document or for a future generation. this allows new host memory controller designs to plan the fl exibility to issue these command instructions. the command format is defined if known at the time this document revision is published. 9.2 identification commands 9.2.1 read identification - re ms (read_id or rems 90h) the read_id command identifies the device manufacturer id and the device id. the command is also referred to as read electronic manufacturer and device signature (rems). read-id (rems) is only supported for backward compatibility and should not be used for new software designs. new software designs should instead make use of the rdid command. the command is initiated by shifting on si the instruction code ?90h? followed by a 24 -bit address of 00000h. following this, t he manufacturer id and the device id are shifted out on so star ting at the falling edge of sck afte r address. the manufacturer id and the device id are always shifted out with the msb first. if t he 24-bit address is set to 000001h, then the device id is read ou t first followed by the manufacturer id. the manufacturer id and de vice id output data toggles between address 000000h and 000001h until terminated by a low to high transition on cs# input. the maximum clock frequency for the read_id command is 108 mhz. document number: 001-98282 rev. *i page 73 of 142 S25FL127S figure 46. read_id command sequence 9.2.2 read identifi cation (rdid 9fh) the read identification (rdid) co mmand provides read access to manufacturer iden tification, device ident ification, and common flash interface (cfi) information. the manufacturer identification is assigned by jedec. the cfi structure is defined by jedec standard. the device identification and cfi values are assigned by cypress. the jedec common flash interface (cfi) specification defines a de vice information structure, which allows a vendor-specified software flash management program (driver) to be used for entir e families of flash devices. software support can then be device-independent, jedec manufacturer id independent, forward an d backward-compatible for the specified flash device families. system vendors can standardize t heir flash drivers for long-term software compatib ility by using the cfi values to configure a family driver from the cfi information of the device in use. any rdid command issued while a program, erase, or write cycle is in progress is ignored and has no effect on execution of the program, erase, or write cycle that is in progress. the rdid instruction is shifted on si. after the last bit of the rdid instruction is sh ifted into the device, a byte of manufac turer identification, two bytes of dev ice identification, extended device identification, and cfi information will be shifted sequent ially out on so. as a whole this information is referred to as id-cfi. see id-cfi address space on page 48 for the detail description of the id-cfi contents. continued shifting of output bey ond the end of the defined id-cfi address spac e will provide undefined data. the rdid command sequence is terminated by driving cs# to the logic high state anytime during data output. the maximum clock frequency for the rdid command is 108 mhz. table 37. read_id values device manufacturer id (hex) device id (hex) S25FL127S 01 17 1 3 2 1 0 9 8 7 6 5 4 0 i n s t r u c t i o n a d d ( 1 ) 2 3 2 1 2 2 1 3 2 0 s c k s i s o h i g h i m p e d a n c e m s b c s s # 9 0 h 3 4 3 3 3 2 3 8 3 7 3 6 3 5 4 3 4 2 4 1 4 0 3 9 4 6 4 5 4 4 s c k s i s o m a n u f a c t u r e i d m s b 1 3 2 0 7 6 5 4 c s s # 4 7 1 3 2 0 7 6 5 4 d e v i c e i d m s b 2 8 2 9 3 1 3 0 document number: 001-98282 rev. *i page 74 of 142 S25FL127S figure 47. read identifica tion (rdid) co mmand sequence 9.2.3 read electronic si gnature (res) (abh) the res command is used to read a single byte electronic signat ure from so. res is only supported for backward compatibility and should not be used for new software designs. new softwa re designs should instead make use of the rdid command. the res instruction is shifted in followed by three dummy bytes onto si. after the last bit of the three dummy bytes are shifte d into the device, a byte of electronic signature will be shifted out of so. each bit is shifted out by the falling edge of sck. the m aximum clock frequency for the res command is 50 mhz. the electronic signature can be read repeatedly by applying multiples of eight clock cycles. the res command sequence is terminated by driving cs# to the logic high state anytime during data output. figure 48. read electronic si gnature (res) command sequence table 38. res values device device id (hex) S25FL127S 17 646 1 3 210 9 8 7 6 5 4 0 31 30 29 28 instruction 1 645 652 34 33 32 655 654 653 sck si so high impedance extended device information cs# 0 1 2 20 21 22 23 24 25 26 644 647 manufacturer / device identification 1 3 210 9 8 7 6 5 4 0 31 30 29 28 instruction 3 dummy bytes 23 21 22 1 32 0 36 35 34 33 32 39 38 37 sck si so high impedance msb electonic id msb 1 32 0 7654 cs# document number: 001-98282 rev. *i page 75 of 142 S25FL127S 9.2.4 read serial flash discover able parameters (rsfdp 5ah) the command is initiated by shifting on si the instruction code ?5ah?, followed by a 24-bit address of 000000h, followed by eig ht dummy cycles. the sfdp bytes are then shift ed out on so starting at the falling edge of sck after the eight dummy cycles. the sfdp bytes are always shifted out with the msb first. if the 24-bit address is set to any other value, the selected location in the sfdp space is the starting point of the dat a read. this enables random access to any pa rameter in the sfdp space. the maximum clock frequency for the rs fdp command is 108 mhz. figure 49. rsfdp command sequence 9.3 register access commands 9.3.1 read status regi ster 1 (rdsr1 05h) the read status register 1 (rdsr1) comman d allows the status register 1 contents to be read from so. the status register 1 contents may be read at any time, even while a program, erase, or write operation is in progress. it is possible to read the st atus register 1 continuously by prov iding multiples of eight clock cycles. the status is updated fo r each eight cycl e read. the maxi mum clock frequency for the rdsr1 (05h) command is 108 mhz. figure 50. read status register 1 (rdsr1) command sequence cs# sck si so phase 76 54 321 023 10 7654 3 210 instruction address dummy cycles data 1 1 3 2 1 0 9 8 7 6 5 4 0 1 4 1 3 1 2 1 1 i n s t r u c t i o n 1 3 2 0 7 6 5 4 s c k s o h i g h i m p e d a n c e m s b s t a t u s r e g i s t e r - 1 o u t s i 1 5 1 8 1 7 1 6 2 2 2 1 2 0 1 9 1 3 2 0 7 6 5 4 m s b s t a t u s r e g i s t e r - 1 o u t 2 3 7 m s b c s s # document number: 001-98282 rev. *i page 76 of 142 S25FL127S 9.3.2 read status regi ster 2 (rdsr2 07h) the read status register (rdsr2) command allows the status r egister 2 contents to be read fr om so. the status register 2 contents may be read at any time, even while a program, erase, or write operation is in progress. it is possible to read the st atus register 2 continuously by prov iding multiples of eight clock cycles. the status is updated fo r each eight cycl e read. the maxi mum clock frequency for the rds r2 command is 108 mhz. figure 51. read status register 2 (rdsr2) command 9.3.3 read configurati on register (rdcr 35h) the read configuration register (rdcr) comma nd allows the configuration register contents to be read from so. it is possible to read the configuration register continuously by providi ng multiples of eight clock cycles. th e configuration re gister contents may be read at any time, even while a program, erase, or write operation is in progress. figure 52. read configuration register (rdcr) command sequence 1 3 210 9 8 7 6 5 4 0 14 13 12 11 instruction 1 32 0 7654 sck so high impedance msb status register-2 out si 15 18 17 16 22 21 20 19 1 32 0 7654 msb status register-2 out 23 7 msb cs# 1 32 0 7654 cs# sclk si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction register read repeat register read document number: 001-98282 rev. *i page 77 of 142 S25FL127S 9.3.4 bank register read (brrd 16h) the read the bank register (brrd) command allows the bank address regi ster contents to be read from so. the instruction is first shifted in from si. then the 8-bit bank register is shifte d out on so. it is possible to read the bank register continuou sly by providing multiples of eight clock cycles. the maximum operating clock frequency for the brrd command is 108 mhz. figure 53. read bank register (brrd) command 9.3.5 bank register write (brwr 17h) the bank register write (brwr) command is used to write address bits above a23, into the bank address register (bar). the command is also used to write the extended address control bit ( extadd) that is also in bar[7 ]. bar provides the high order addresses needed by devices having more than 128 mbits (16 mb ytes), when using 3-byte add ress commands without extended addressing enabled (bar[7] extadd = 0). because this command is part of the addressing method and is not changing data in the flash memory, this command does not r equire the wren command to precede it. the brwr instruction is entered, followed by the data byte on si. the bank register is one data byte in length. the brwr command has no effect on the p_err, e_err or wip bits of the status and configuratio n registers. any bank address bit reserved for the future should always be written as a 0. figure 54. bank regist er write (brwr) command 7 6 5 4 7 6 5 4 3 2 1 0 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 high impedance h i g h i m p e d a n c e 7 6 5 4 7 6 5 4 3 2 1 0 3 2 1 0 7 6 5 4 7 6 5 4 3 2 1 0 3 2 1 0 bank register out b a n k r e g i s t e r o u t bank register out b a n k r e g i s t e r o u t instruction i n s t r u c t i o n msb m s b msb m s b msb m s b 7 msb m s b cs# c s # sck s c k si s i so s o instruction bank register in 1 3 210 9 8 7 6 5 4 0 14 13 12 11 15 1 32 0 7654 sck si so msb high impedance cs# 0 1 7 6 5 4 3 2 msb document number: 001-98282 rev. *i page 78 of 142 S25FL127S 9.3.6 bank register access (brac b9h) the bank register read and write commands provide full access to the bank address register (bar) but they are both commands that are not present in legacy spi memory devices. host system spi memory controlle r interfaces may not be able to easily suppo rt such new commands. the bank register access (brac) command us es the same command code and format as the deep power down (dpd) command that is available in legacy spi memories. t he fl-s family does not support a dpd feature but assigns this legacy command code to the brac command to enable write access to the bank address register for legacy systems that are able to send the legacy dpd (b9h) command. when the brac command is sent, the fl-s family device will then interpret an immediately following write register (wrr) command as a write to the lower address bits of the bar. a wren command is not used between the brac and wrr commands. only the lower two bits of the first data byte following the wrr command code are used to load bar[1:0]. the upper bits of that byte and the content of the optional wrr comma nd second data byte are ignored. following the wrr command the access to bar is closed and the device interface returns to the standby state. the co mbined brac followed by wrr command sequence has no affect on the value of the extadd bit (bar[7]). commands other than wrr may immediately follow brac and exec ute normally. however, any command other than wrr, or any other sequence in which cs# goes low and returns high, following a brac command, will close the access to bar and return to the normal interpretation of a wrr command as a write to status register 1 and the configuration register. the brac + wrr sequence is allowed only when the device is in standby, program suspend, or erase suspend states. this command sequence is illegal when the device is performing an embedded algorithm or when t he program (p_err) or erase (e_err) status bits are set to 1. figure 55. brac (b9h) command sequence 9.3.7 write registers (wrr 01h) the write registers (wrr) command allows new values to be writ ten to status register 1, configuration register, and status register 2. before the write registers (wrr) command can be accepted by the devic e, a write enable (wren) command must be received. after the write enable (wren) command has been dec oded successfully, the device will set the write enable latch (wel) in the status register to enable any write operations. the write registers (wrr) command is entered by sh ifting the instruction and the data bytes on si. the write registers (wrr) command will set th e p_err or e_err bits if there is a failu re in the wrr operation. any status or configuration register bit that is: ? reserved for the future, must be written as a 0 ? read only, is not affected by the value written to that bit ? otp, may be written to 1 but, if the value is alre ady 1, it cannot be written to 0, it will remain 1. cs# must be driven to the logic high stat e after the eighth, sixteenth, or twenty-f ourth bit of data has been latched. if not, the write registers (wrr) command is not ex ecuted. if cs# is driven high af ter the eighth cycle then only t he status register 1 is writte n; after the sixteenth cycle both the status and configuration regist ers are written; after the twenty fourth cycle the status reg ister 1, configuration register, and status register 2 are written. when the co nfiguration register quad bi t cr[1] is 1, only the wrr command formats with 16 or 24 data bits may be used. 1 3 27 6 5 4 0 instruction sck so high impedance si cs# 0 1 7 6 5 4 3 2 msb document number: 001-98282 rev. *i page 79 of 142 S25FL127S as soon as cs# is driven to the logic hi gh state, the self-tim ed write registers (wrr) operation is initiated. while the write registers (wrr) operation is in progress, t he status register may still be read to c heck the value of the write-in progress (wi p) bit. the write-in progress (wip) bit is a 1 during the self-timed writ e registers (wrr) operation, and is a 0 when it is completed. when only changing the value of volatile bi ts, the operation is completed in t cs time (the wip bit will be 0 before a status read can be completed). when changing non-volatile bits , the wrr operation is completed in t w time. when the write registers (wrr) operation is completed, the write enable latch (wel) is set to a 0. the maximum clock frequency for the wrr command is 108 mhz. figure 56. write registers (wrr) command sequence ? 8 data bits figure 57. write registers (wrr) command sequence ? 16 data bits figure 58. write registers (wrr 01h) command sequence ? 24 data bits the write registers (wrr) command allows th e user to change the values of the block protect (bp2, bp1, and bp0) bits to define the size of the area that is to be treated as read-only. the writ e registers (wrr) command also a llows the user to set the stat us register write disable (srwd) bit to a 1 or a 0. the status register write disable (srwd) bit and write protect (wp#) signal al low the bp bits to be hardware protected. instruction status register in 1 3 210 9 8 7 6 5 4 0 14 13 12 11 15 1 32 0 7654 sck si so msb high impedance cs# i i n s t r u c t i o n s t a t u s r e g i s t e r i n 1 3 2 1 0 9 8 7 6 5 4 0 1 4 1 3 1 2 1 1 1 5 1 3 2 0 7 6 5 4 s c k s i s o m s b h i g h i m p e d a n c e c s s # c o n f i g u r a t i o n r e g i s t e r i n 1 8 1 7 1 6 2 2 2 1 2 0 1 9 2 3 1 3 2 0 7 6 5 4 m s b cs# sck si so phase 765432107654321076543210 instruction input status register-1 input status register-2 document number: 001-98282 rev. *i page 80 of 142 S25FL127S when the status register write disable (srw d) bit of the status register is a 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (wel) bit has previous ly been set by a write enable (wren) command, regardless of the whether write protect (wp#) signal is driven to the logic high or logic low state. when the status register write disable (srw d) bit of the status register is set to a 1, two cases need to be considered, depend ing on the state of write protect (wp#): ? if write protect (wp#) signal is driven to the logic high state, it is possible to write to the status and configuration regist ers provided that the write enable latch (wel) bit has previous ly been set to a 1 by initiating a write enable (wren) command. ? if write protect (wp#) signal is driven to the logic low state, it is not possible to write to the status and configuration registers even if the write enable latch (wel) bit has previo usly been set to a 1 by a write enable (wren) command. attempts to write to the status and configuration register s are rejected, and are not accepted for execution. as a consequence, all the data bytes in the memory area that are protected by the block protect (bp2, bp1, bp0) bits of the status register, are also hardware protected by wp#. the wp# hardware protection can be provided: ? by setting the status register write disable (srwd) bit afte r driving write protect (wp#) signal to the logic low state; ? or by driving write protect (wp#) signal to the logic low state af ter setting the status register write disable (srwd) bit to a 1. the only way to release the hardware protec tion is to pull the write protect (wp#) sig nal to the logic high state. if wp# is permanently tied high, hardware protection of the bp bits can never be activated. notes: 1. the status register originally shows 00h when the de vice is first shipped from cypress to the customer. 2. hardware protection is disabled when quad mode is enabled (quad bit = 1 in configuration register). wp# becomes io2; therefor e, it cannot be utilized. the wrr command has an alternate function of loading the bank address register if the command immediately follows a brac command. see bank register access (brac b9h) on page 78 . table 39. block protection modes wp# srwd bit mode write protection of registers memory content protected area unprotected area 11 software protected status and configuration registers are writable (if wren command has set the wel bit). the values in the srwd, bp2, bp1, and bp0 bits and those in the confi guration register and status register 2 can be changed. protected against page program, quad input program, sector erase, and bulk erase ready to accept page program, quad input program and sector erase commands 10 00 01 hardware protected status and configuration registers are hardware write protecte d. the values in the srwd, bp2, bp1, and bp0 bits and those in the configuration register and status register 2 cannot be changed. protected against page program, sector erase, and bulk erase ready to accept page program or erase commands document number: 001-98282 rev. *i page 81 of 142 S25FL127S 9.3.8 write enable (wren 06h) the write enable (wren) command sets the write enable latch (w el) bit of the status register 1 (sr1[1]) to a 1. the write enable latch (wel) bit must be set to a 1 by issuing the wr ite enable (wren) command to enable write, program and erase commands. cs# must be driven into the logic high st ate after the eighth bit of the instruction byte has been latched in on si. without cs # being driven to the logic high state after the eighth bit of the instru ction byte has been latched in on si, the writ e enable operati on will not be executed. figure 59. write enable (wren) command sequence 9.3.9 write disable (wrdi 04h) the write disable (wrdi) command sets the write enable latch (wel) bit of the status register 1 (sr1[1]) to a 0. the write enable latch (wel) bit may be set to a 0 by issuing the write disable (wrdi) command to disable page program (pp), sector erase (se), bulk erase (be), writ e registers (wrr), otp program (otpp), and other commands, that require wel be set to 1 for execution. the wrdi command can be used by the user to protect memory ar eas against inadvertent writes that can possibly corrupt the contents of the memory. the wrdi command is ignored during an embedded operation while wip bit =1. cs# must be driven into the logic high st ate after the eighth bit of the instruction byte has been latched in on si. without cs # being driven to the logic high state after the eighth bit of the instru ction byte has been latched in on si, the write disable operat ion will not be executed. figure 60. write disable (wrdi) command sequence 3 27 6 5 4 0 instruction sck si 1 cs# 3 27 6 5 4 0 instruction sck si 1 cs# document number: 001-98282 rev. *i page 82 of 142 S25FL127S 9.3.10 clear status register (clsr 30h) the clear status register command resets bi t sr1[5] (erase fail flag) and bit sr1[6] (p rogram fail flag). it is not necessary t o set the wel bit before the clear sr command is executed. the cle ar sr command will be accepted even when the device remains busy with wip set to 1, as the device doe s remain busy when either error bit is set. the wel bit will be unchanged after this command is executed. figure 61. clear status register (clsr) command sequence 9.3.11 ecc status regi ster read (eccrd 18h) to read the ecc status register, the command is followed by the ecc unit (32 bit) addres s, the four least significant bits (lsb ) of address must be set to ze ro. this is followed by eight dummy cycles. then the 8-bit content s of the ecc register, for the ecc u nit selected, are shifted out on so 16 times, once for each byte in the ecc unit. if cs# remains low the next ecc unit status is se nt through so 16 times, once for each byte in the ecc unit, this continues until cs# goes hi gh. the maximum operating clock frequency for the ecc read command is 133 mhz. see section 9.5.1.1 automatic ecc on page 93 for details on ecc unit. figure 62. ecc status register read command sequence 3 2 7 6 5 4 0 i n s t r u c t i o n sck si 1 cs# 13 210 9 8 7 6 5 4 039 38 37 3 6 instructio n 32-bit address 31 29 30 1 32 0 1 32 0 765 4 44 43 42 41 40 47 46 4 5 1 32 0 765 4 dummy byt e 52 51 50 49 48 55 54 5 3 data out 1 data out 2 sck si so msb high impedance 7 msb c s# 1 32 0 765 4 document number: 001-98282 rev. *i page 83 of 142 S25FL127S 9.3.12 autoboot spi devices normally require 32 or more cycles of command and address shifting to initiate a read command. and, in order to rea d boot code from an spi device, the host me mory controller or processor must supply the read command from a hardwired state machine or from some host processor internal rom code. parallel nor devices need only an initial address, supplied in para llel in a single cycle, and in itial access time to start rea ding boot code. the autoboot feature allows the host memory controller to take boot code from an fl-s family dev ice immediately after the end o f reset, without having to send a read command. this saves 32 or more cycles and simplifies the logic needed to initiate the read ing of boot code. ? as part of the power up reset, hardware reset, or command re set process the autoboot featur e automatically starts a read access from a pre-specified address. at the time the reset pr ocess is completed, the device is ready to deliver code from the starting address. the host memory controller only needs to drive cs# signal from high to low and begin toggling the sck signal. the fl-s family device will delay code output fo r a pre-specified number of clock cycles before code streams out. ? the auto boot start delay (absd) field of the autoboot regi ster specifies the in itial delay if any is needed by the host. ? the host cannot send commands during this time. ? if absd = 0, the maximum sck frequency is 50 mhz. ? if absd > 0, the maximum sck frequency is 108 mhz if the quad bit cr1[1] is 0 or 108 mhz if the quad bit is set to 1. ? the starting address of the boot code is selected by the value programmed into the autoboot start address (absa) field of the autoboot register which specifies a 512-byte boun dary aligned location; the default address is 00000000h. ? data will continuously shift out until cs# returns high. ? at any point after the first data byte is transferred, when cs# returns high, the spi device will reset to standard spi mode; able to accept normal command operations. ? a minimum of 1 byte must be transferred. ? autoboot mode will not initiate again unt il another power cycle or a reset occurs. ? an autoboot enable bit (abe) is set to enable the autoboot feature. the autoboot register bits are non-volatile and provide: ? the starting address (512-byte boundary), set by the autoboot start address (absa). the size of the absa field is 23 bits for devices up to 32-gbit. ? the number of initial delay cycles, set by the autoboot start delay ( absd) 8-bit count value. ? the autoboot enable. if the configuration register quad bit cr1[1] is set to 1, th e boot code will be provided 4 bits per cycle in the same manner a s a read quad out command. if the quad bit is 0 the code is del ivered serially in the same manner as a read command. figure 63. autoboot sequence (cr1[1]=0) -- -n+2 n+1 n - - - 0n+7 n+6 n+5 n+ 4 wait state tw s 1 32 0 765 4 n+9 n+ 8 sck si so high impedance msb data out 1 data out 2 7 ms b cs# n+ 3 don?t care or high impedance document number: 001-98282 rev. *i page 84 of 142 S25FL127S figure 64. autoboot sequence (cr1[1]=1) 9.3.13 autoboot regist er read (abrd 14h) the autoboot register read command is shifted into si. then the 32-bit autoboot register is shifted out on so, least significan t byte first, most significant bit of each byte first. it is po ssible to read the autoboot regist er continuously by providing mul tiples of 32 clock cycles. if the quad bit cr1[1] is clea red to 0, the maximum operating clock frequency for abrd command is 108 mhz. if the quad bit cr1[1] is set to 1, the maximum operating clock frequency for abrd command is 108 mhz. figure 65. autoboot re gister read (abrd) command 9.3.14 autoboot register write (abwr 15h) before the abwr command can be accepted, a write enable (wre n) command must be issued and decoded by the device, which sets the write enable latch (wel) in the stat us register to enable any write operations. the abwr command is entered by shifting the instruction and the data bytes on si, least sign ificant byte first, most significan t bit of each byte first. the abwr data is 32 bits in length. the abwr command has status reported in st atus register 1 as both an erase and a programming operation. an e_err or a p_err may be set depending on whether the erase or pr ogramming phase of updat ing the register fails. cs# must be driven to the logic high state after the 32nd bit of data has been latched. if not, the abwr command is not execute d. as soon as cs# is driven to the logic hi gh state, the self-tim ed abwr operation is initiated. while the abwr operation is in progress, status register 1 may be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bit is a 1 during the self-timed abwr operation, and is a 0 when it is completed. when the abwr cycle is completed, the write enable latch (wel) is set to a 0. the maximum clock frequency for the abwr command is 108 mhz. - - -n+2 n+1 n - - - 0 n+7 n+6 n+5 n+4 wait state tws 5 51 1 5151 n+9 n+8 sck io0 io1 high impedance data out 1 5 cs# n+3 4 4 40 0 040 high impedance 4 6 62 2 6262 high impedance 6 io2 7 73 3 7373 high impedance msb 7 io3 24 25 7 6 5 4 26 1 3 210 9 8 7 6 5 4 0 38 37 11 instruction sck so high impedance msb autoboot register si 39 40 msb 7 cs# 0 1 7 6 5 4 3 2 msb document number: 001-98282 rev. *i page 85 of 142 S25FL127S figure 66. autoboot regi ster write (abwr) command 9.4 read memory array commands read commands for the main flash array provide many options for prior generation spi compatib ility or enhanced performance spi: ? some commands transfer address one bit per rising edge of sck and return data 1, 2, or 4 bits of data per rising edge of sck. these are called read or fast read for 1 bit data; dual output read for 2 bit data, and quad output for 4 bit data. ? some commands transfer both address and data 2 or 4 bits per rising edge of sck. these are called dual i/o for 2 bit and quad i/o for 4 bit. all of these commands begin with an instru ction code that is transferred one bit per sck rising edge. the instruction is follow ed by either a 3- or 4-byte address. commands transferring address or data 2 or 4 bits per clock edge are called multiple i/o (mio) commands. for fl-s family devices at 256 mbits or higher densit y, the traditional spi 3-byte addresses are unable to directly address all locations in the memory array. these device have a bank address register that is us ed with 3-byte address commands to supply the high order address bits beyo nd the address from the host system. the def ault bank address is 0. commands are provided to load and read the bank address register. these devices may also be configured to take a 4-byte address from the hos t system with the traditional 3-byte address commands. the 4-byte address mode for traditi onal commands is activated by setting t he external address (extadd) bit in the bank address register to 1. in the fl127s, higher order address bits above a23 in the 4-by te address commands, commands using extended address mode, and th e bank address register are not relevant and are ignored because the flash array is only 128 mbits in size. the quad i/o commands provide a performanc e improvement option controlled by mode bits that are sent following the address bits. the mode bits indicate whether the command following the end of the current read will be another read of the same type, without an instruction at the beginning of the read. these mode bits give the option to eliminate the instruction cycles when d oing a series of quad i/o read accesses. some commands require delay cycles following the address or mode bits to allow time to a ccess the memory a rray. the delay cycles are traditionally called dummy cycles. the dummy cycles are ignored by the memory thus any da ta provided by the host during these cycles is ?don?t care? and the host may also leav e the si signal at high impedance during the dummy cycles. when m io commands are used the host must stop driving the io signals (out puts are high impedance) before the end of last dummy cycle. th e number of dummy cycles varies with the sck frequency or perform ance option selected via the co nfiguration register 1 (cr1) latency code (lc). dummy cycles are meas ured from sck falling edge to next sck fa lling edge. spi outputs are traditionally driven to a new value on the falling edge of each sck. zero dummy cycles means the returning data is driven by the memory on th e same falling edge of sck that the host stops driving address or mode bits. each read command ends when cs# is returned high at any point during data return. cs# must not be returned high during the mode or dummy cycles before data returns as this may cause mode bi ts to be captured in correctly; making it indeterminate as to whether the device remains in enhanced high performance read mode. instruction autoboot register 1 3 210 9 8 7 6 5 4 0 38 37 36 39 24 25 7 6 5 27 26 sck si so msb high impedance cs# 0 1 7 6 5 4 3 2 msb document number: 001-98282 rev. *i page 86 of 142 S25FL127S 9.4.1 read (read 03h or 4read 13h) the instruction ? 03h (extadd=0) is followed by a 3-byte address (a23-a0) or ? 03h (extadd=1) is followed by a 4-byte address (a31-a0) or ? 13h is followed by a 4-byte address (a31-a0) then the memory contents, at the address given, are shifted out on so. the maximum operating clock frequency for the read command is 50 mhz. the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. figure 67. read command sequence (read 03h or 13h) note: a = msb of address = 23 for extadd=0, or 31 for extadd=1 or command 13h. 9.4.2 fast read (fast_read 0bh or 4fast_read 0ch) the instruction ? 0bh (extadd=0) is followed by a 3-byte address (a23-a0) or ? 0bh (extadd=1) is followed by a 4-byte address (a31-a0) or ? 0ch is followed by a 4-byte address (a31-a0) the address is followed by zero or eight dummy cycles depending on the la tency code set in the configuration register. the dumm y cycles allow the device internal circuits additional time for accessing the initial address locati on. during the dummy cycles t he data value on so is ?don?t care? and may be high impedance. then t he memory contents, at the address given, are shifted out on so. the maximum operating clock frequency for fast read command is 108 mhz. the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. figure 68. fast read (fast_read 0bh or 0ch) command sequence with read latency cs# sck si so phase 76 54 321 0a 10 7654321076543210 instruction address data 1 data n cs# sck si so phase 76 54 321 0a 10 7 654 3210 instruction address dummy cycles data 1 document number: 001-98282 rev. *i page 87 of 142 S25FL127S figure 69. fast read command (fast_read 0bh or 0ch) sequence without read latency 9.4.3 dual output read (dor 3bh or 4dor 3ch) the instruction ? 3bh (extadd=0) is followed by a 3-byte address (a23-a0) or ? 3bh (extadd=1) is followed by a 4-byte address (a31-a0) or ? 3ch is followed by a 4-byte address (a31-a0) then the memory contents, at the address given, is shifted out tw o bits at a time through io0 (si) and io1 (so). two bits are s hifted out at the sck frequency by the falling edge of the sck signal. the maximum operating clock frequency for the dual output read command is 108 mhz. for dual output read commands, there are zero or eight dummy cycles required afte r the last address bit is sh ifted into si before data be gins shifting out of io0 an d io1. this latency period (i.e., dummy cycles) allo ws the device?s internal circuitry enough time to read from the initial address. d uring the dummy cycles, the data value on si is a ?don?t care? and may be high impedance. the number of dummy cycles is determined by the frequency of sck (refer to table 22, latency codes on page 53 ). the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. figure 70. dual output read command sequence (3-byte address, 3bh [extadd=0], lc=10b) figure 71. dual output read command sequence (4-byte address, 3ch or 3bh [extadd=1, lc=10b]) cs# sck si so phase 76 54 321 0a 10 7654321076543210 instruction address data 1 data n cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 23 22 21 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 instruction address 8 dummy cycles data 1 data 2 cs# sck io0 io1 phase 76 5432 103130290 64 2064 20 75 3175 31 instruction address 8 dummy cycles data 1 data 2 document number: 001-98282 rev. *i page 88 of 142 S25FL127S figure 72. dual output read command sequence (4-byte address, 3ch or 3bh [extadd=1, lc=11b]) 9.4.4 quad output read (qor 6bh or 4qor 6ch) the instruction ? 6bh (extadd=0) is followed by a 3-byte address (a23-a0) or ? 6bh (extadd=1) is followed by a 4-byte address (a31-a0) or ? 6ch is followed by a 4-byte address (a31-a0) then the memory contents, at the address given, is shifted out four bits at a time through io0-io3. each nibble (4 bits) is shi fted out at the sck frequency by the falling edge of the sck signal. the maximum operating clock frequency for quad output read command is 108 mhz. for quad output read mode, there may be dummy cycles required after the last address bit is shifted into si befor e data begins shifting out of io0-io3. this latency pe riod (i.e., dummy cycles) allows the device?s internal circuitry enough time to set up for the initial address. during the dummy cycles, th e data value on io0-io3 is a ?don?t care? and may be high impedance. the number of dummy cycles is determined by the frequency of sck (refer to table 22, latency codes on page 53 ). the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. the quad bit of configuration register must be set (cr bit1=1) to enable the quad mode capability. figure 73. quad output read (qor 6bh or 4qor 6ch) command sequence with read latency notes: 1. a = msb of address = a23 for extadd = 0, or a31 for extadd=1 or command 6ch. 2. lc = 01b shown. cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 31 30 29 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 instruction address data 1 data 2 0 1 2 3 4 5 6 7 8 30 31 32 33 34 35 36 37 38 39 40 41 42 43 instruction 24 bit address 8 dummy cycles data 1 data 2 7 6 5 4 3 2 1 0 23 1 0 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 cs# sclk io0 io1 io2 io3 document number: 001-98282 rev. *i page 89 of 142 S25FL127S figure 74. quad output read (qor 6bh or 4qor 6ch) command sequence without read latency notes: 1. a = msb of address = a23 for extadd = 0, or a31 for extadd = 1 or command 6ch. 2. lc = 11b shown. 9.4.5 dual i/o read (d ior bbh or 4dior bch) the instruction ? bbh (extadd=0) is followed by a 3-byte address (a23-a0) or ? bbh (extadd=1) is followed by a 4-byte address (a31-a0) or ? bch is followed by a 4-byte address (a31-a0) the dual i/o read commands improve throughput with two i/o signals ? io0 (si) and io1 (so). it is similar to the dual output read command but takes input of the address two bits per sck risi ng edge. in some applications, the reduced address input time might allow for code execution in place (xip) i.e. directly from the memory device. the maximum operating clock frequency for dual i/o read is 108 mhz. for the dual i/o read command, there is a la tency required after the last address bits are shifted into si and so before data b egins shifting out of io0 and io1. this latency period (dummy cycles) allows the device internal ci rcuitry enough time to access data at the initial address. duri ng the dummy cycles, the data value on si and so are ?don?t care? and may be high imp edance. the number of dummy cycles is determined by the frequency of sck ( table 22, latency codes on page 53 ). the number of dummy cycles is set by the lc bits in the configuration register (cr1). the latency code table provides cycl es for mode bits so a series of dual i/o re ad commands may eliminat e the 8-bit instruction after the first dual i/o read command sends a mode bit pattern of axh that indicates the following command will also be a dual i/o read command. the first dual i/o read command in a series starts with the 8-bit instruction, follow ed by address, followed by f our cycles of mode bits, followed by a latency period. if the mode bit pattern is axh the next co mmand is assumed to be an addition al dual i/o read command that does not provide instruction bits. that command starts with address, followed by mode bits, followed by latency. the enhanced high performance feature removes the need for the inst ruction sequence and greatly improves code execution (xip). the upper nibble (bits 7-4) of the mode bits control the length of the next dual i/o read command through the inclusion or excl usion of the first byte instruction code. the lower nibble (bits 3-0) of the mode bits are ?don?t care? (?x?) and may be high impedan ce. if the mode bits equal axh, then the device remains in dual i/o enh anced high performance read mode and the next address can be entered (after cs# is raised high and then asserted lo w) without the bbh or bch in struction, as shown in figure 77 ; thus, eliminating eight cycles for the command sequence. the following sequences w ill release the device from dual i/o enhanced high performance read mode; after which, the device can accept standard spi commands: 1. during the dual i/o enhanced high performance command sequence, if the mode bits are any value other than axh, then the next time cs# is raised high the device will be released from dual i/o read enhanced high performance read mode. 2. during any operation, if cs# toggles high to low to high fo r eight cycles (or less) and data input (io0 and io1) are not set for a valid instruction sequence, then the device will be re leased from dual i/o enhanced high performance read mode. note that the four mode bit cycles are part of the device?s internal circuitry latency time to access the initial address after the last address cycle that is clo cked into io0 (si) and io1 (so). 0 1 2 3 4 5 6 7 8 38 39 40 41 42 43 44 45 46 47 48 49 50 51 instruction 32 bit address 8 dummy cycles data 1 data 2 7 6 5 4 3 2 1 0 31 1 0 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 cs# sclk io0 io1 io2 io3 document number: 001-98282 rev. *i page 90 of 142 S25FL127S it is important that the i/o signals be set to high-impedance at or before the falling edge of t he first data out clock. at hig her clock speeds the time available to turn off the host outputs before th e memory device begins to drive (b us turn around) is diminished . it is allowed and may be helpful in preventing i/o signal contention, for the host system to turn of f the i/o signal outputs (make th em high impedance) during the last two ?don?t care? mode cycles or during any dummy cycles. following the latency period the memory conten t, at the address given, is shifted out two bits at a time through io0 (si) and i o1 (so). two bits are shifted out at the sck frequency at the falling edge of sck signal. the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. cs# should not be driven high during mode or dummy bi ts as this may make the mode bits indeterminate. figure 75. dual i/o read command sequ ence (3-byte address, bbh [extadd=0]) figure 76. dual i/o read command sequence (4-byte address, bch or bbh [extadd=1]) note: 1. least significant 4 bits of mode are don?t care and it is op tional for the host to drive thes e bits. the host may turn off dr ive during these cycles to increase bus turn around time between mode bits from host and returning data from the memory. figure 77. continuous dual i/o read command sequence (4-byte address, bch or bbh [extadd=1]) note: 1. least significant 4 bits of mode are don?t care and it is op tional for the host to drive thes e bits. the host may turn off dr ive during these cycles to increase bus turn around time between mode bits from host and returning data from the memory. cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 22 2 0 6 4 2 0 6 4 2 0 6 4 2 0 23 3 1 7 5 3 1 7 5 3 1 7 5 3 1 instruction address mode dum data 1 data 2 cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 30 2 0 6 4 2 0 6 4 2 0 6 4 2 0 31 3 1 7 5 3 1 7 5 3 1 7 5 3 1 instruction address mode dum data 1 data 2 cs# sck io0 io1 phase 6 4 2 0 30 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 31 3 1 7 5 3 1 7 5 3 1 7 5 3 1 data n address mode dum data 1 data 2 document number: 001-98282 rev. *i page 91 of 142 S25FL127S 9.4.6 quad i/o read (q ior ebh or 4qior ech) the instruction ? ebh (extadd=0) is followed by a 3-byte address (a23-a0) or ? ebh (extadd=1) is followed by a 4-byte address (a31-a0) or ? ech is followed by a 4-byte address (a31-a0) the quad i/o read command improves throughput with four i/o signals ? io0-io3. it is similar to the quad output read command but allows input of the address bits four bits per serial sck clock. in some applications, the reduced instruction overhead mig ht allow for code execution (xip) directly from fl-s family devices. the quad bit of the configuration register must be set (cr bit1=1) to enable the quad capability of fl-s family devices. the maximum operating clock frequency for quad i/o read is 108 mhz. for the quad i/o read command, there is a latency required after the m ode bits (described below) before data begins shifting ou t of io0-io3. this latency period (i.e., dummy cycles) allows the de vice?s internal circuitry enough time to access data at the init ial address. during latency cycles, the data value on io0-io3 are ?don?t care? and may be high impedance. the number of dummy cycles is determined by the frequency of sck and the latency code table (refer to table 22, latency codes on page 53 ). the number of dummy cycles is set by the lc bi ts in the configuration regist er (cr1). however, both late ncy code tables use the sam e latency values for the quad i/o read command. following the latency period, the memory co ntents at the address given, is shifted out four bits at a time through io0-io3. eac h nibble (4 bits) is shifted out at the sck fr equency by the falling edge of the sck signal. the address can start at any byte location of the memory array. the address is automatically incremented to the next higher add ress in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read instruction and address 000000h provided. when the highest add ress is reached, the address counter will wrap around and roll ba ck to 000000h, allowing the read sequence to be continued indefinitely. address jumps can be done without the need for additional quad i/o read instructions. this is controlled through the setting of the mode bits (after the address sequence, as shown in figure 78 on page 92 or figure 80 on page 92 ). this added feature removes the need for the instruction sequenc e and greatly improves code exec ution (xip). the upper nibble (bits 7-4) of the mode bits c ontrol the length of the next quad i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower ni bble (bits 3-0) of the mode bits are ?don?t care? (?x?). if the mode bits equal axh, then the device remains in quad i/o high performance read mode and the next address can be entered (after cs# is raised high and then asserted low) wi thout requiring the ebh or ech instruction, as shown in figure 79 on page 92 or figure 81 on page 92 ; thus, eliminating eight cycles for the command sequence. the following sequences will release the device from quad i/o hi gh performance read mode; after which, the device can accept standard spi commands: 1. during the quad i/o read command sequence, if the mode bits are any value other than axh, then the next time cs# is raised high the device will be released from quad i/o high performance read mode. 2. during any operation, if cs# toggles high to low to high for eight cycles (or less) and data input (io0-io3) are not set for a valid instruction sequence, then t he device will be released from quad i/o high performance read mode. note that the two mode bit clock cycles an d additional wait states (i.e., dummy cycles) allow the device?s internal circuitry l atency time to access the initial addr ess after the last address cycle that is clocked into io0-io3. it is important that the io0-io3 signals be set to high-impedanc e at or before the falling edge of the first data out clock. at higher clock speeds the time available to turn off the host outputs befo re the memory device begins to drive (bus turn around) is dimi nished. it is allowed and may be helpful in preventing io0-io3 signal cont ention, for the host system to turn off the io0-io3 signal ou tputs (make them high impedance) during the last ?don ?t care? mode cycle or during any dummy cycles. cs# should not be driven high during mode or dummy bi ts as this may make the mode bits indeterminate. document number: 001-98282 rev. *i page 92 of 142 S25FL127S figure 78. quad i/o read command sequence (3-byte address, ebh [extadd=0]) figure 79. continuous quad i/o read command sequence (3-byte address) figure 80. quad i/o read command sequence (4-byte address, ech or ebh [extadd=1]) figure 81. continuous quad i/o read command sequence (4-byte address) cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 20 4 0 4 0 4 0 4 0 4 0 4 0 21 5 1 5 1 5 1 5 1 5 1 5 1 22 6 2 6 2 6 2 6 2 6 2 6 2 23 7 3 7 3 7 3 7 3 7 3 7 3 instruction address mode dummy d1 d2 d3 d4 cs# sck io0 io1 io2 io3 phase 4 0 4 0 20 4 0 4 0 4 0 4 0 6 4 2 0 5 1 5 1 21 5 1 5 1 5 1 5 1 7 5 3 1 6 2 6 2 22 6 2 6 2 6 2 6 1 7 5 3 1 7 3 7 3 23 7 3 7 3 7 3 7 1 7 5 3 1 dn-1 dn address mode dummy d1 d2 d3 d4 cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 28 4 0 4 0 4 0 4 0 4 0 4 0 29 5 1 5 1 5 1 5 1 5 1 5 1 30 6 2 6 2 6 2 6 2 6 2 6 2 31 7 3 7 3 7 3 7 3 7 3 7 3 instruction address mode dummy d1 d2 d3 d4 cs# sck io0 io1 io2 io3 phase 4 0 4 0 28 4 0 4 0 4 0 4 0 6 4 2 0 5 1 5 1 29 5 1 5 1 5 1 5 1 7 5 3 1 6 2 6 2 30 6 2 6 2 6 2 6 1 7 5 3 1 7 3 7 3 31 7 3 7 3 7 3 7 1 7 5 3 1 dn-1 dn address mode dummy d1 d2 d3 d4 document number: 001-98282 rev. *i page 93 of 142 S25FL127S 9.5 program flash array commands 9.5.1 program granularity 9.5.1.1 automatic ecc each 16 byte aligned and 16 byte length programming block has an automatic error correction code (ecc) value. the data block plus ecc form an ecc unit. in combination with error detection a nd correction (edc) logic the ecc is used to detect and correct any single bit error found during a read access. when data is fi rst programmed within an ecc unit the ecc value is set for the entire ecc unit. if the same ecc unit is programmed more than once the ecc value is changed to disable the error detection and correction (edc) function. a sector erase is needed to again enable automatic ecc on that programming block. the 16 byte program block is the smallest program granularity on which automatic ecc is enabled. these are automatic operations transparent to the user. the transparency of the au tomatic ecc feature enhances data accuracy for typical programming operations which write data once to ea ch ecc unit but, facilitates software compatibility to previous generations of fl-s family of products by allowing for single byte programming and bit walking in which the same ecc unit is programmed more than once. when an ecc unit has automatic ecc disabled, edc is not done on data read from the ecc unit location. an ecc status register is provided for determining if ecc is en abled on an ecc unit and whether any errors have been detected and corrected in the ecc unit data or the ecc (see section 7.6.6 ecc status register (eccsr) on page 56 .) the ecc status register read (eccrd) command is used to read the ecc status on any ecc unit. edc is applied to all parts of the flash address spaces other th an registers. an ecc is calculated for each group of bytes prot ected and the ecc is stored in a hidden area related to the group of bytes. the group of protected bytes and the related ecc are toge ther called an ecc unit. ecc is calculated for each 16 byte aligned and length ecc unit. ? single bit edc is supported with 8 ecc bits per ecc unit, plus 1 bit for an ecc disable flag. ? sector erase resets all ecc bits and ecc disable flags in a sector to the default state (enabled). ? ecc is programmed as part of th e standard program commands operation. ? ecc is disabled automatically if multiple programming operations are done on the same ecc unit. ? single byte programming or bit walking is allowed but disables ecc on the second program to the same 16-byte ecc unit. ? the ecc disable flag is programmed when ecc is disabled. ? to re-enable ecc for an ecc unit that has been disabled, th e sector that includes th e ecc unit must be erased. ? to ensure the best data integrity provid ed by edc, each ecc unit should be progra mmed only once so that ecc is stored for that unit and not disabled. ? the calculation, programming, and disa bling of ecc is done automat ically as part of a programming operation. the detection and correction, if needed, is done automatically as part of read operations. the host system sees only corrected data from a read operation. ? ecc protects the otp region - however a second program op eration on the same ecc unit will disable ecc permanently on that ecc unit (otp is one time programmable, hence an er ase operation to re-enable the ecc enable/indicator bit is prohibited). 9.5.1.2 page programming page programming is done by loading a page buffer with data to be programmed and issuing a programming command to move data from the buffer to the memory array. this sets an upper limit on the amount of data that can be programmed with a single programming command. page programming allows up to a page size (either 256 or 512 bytes) to be programmed in one operation. the page size is determined by a configuration bit (sr2[6]). th e page is aligned on the page size address boundary. it is possi ble to program from one bit up to a page size in each page programming operation. it is recommended that a multiple of 16-byte length and aligned program blocks be written. for the very best perfor mance, programming should be done in full, aligned, pages of 512 bytes aligned on 512-byte boundaries with each page being programmed only once. document number: 001-98282 rev. *i page 94 of 142 S25FL127S 9.5.1.3 single byte programming single byte programming allows full back ward compatibility to the standard spi pa ge programming (pp) command by allowing a single byte to be programmed anywhere in the memory array. while single byte programming is supported, this will disable automatic ecc on the 16 byte ecc unit where the byte is located. 9.5.2 page program ( pp 02h or 4pp 12h) the page program (pp) commands allows bytes to be programmed in the memory (changing bits from 1 to 0). before the page program (pp) commands can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) command has been decoded successfully, the device sets the write enable latch (wel) in the status register to e nable any write operations. the instruction ? 02h (extadd=0) is followed by a 3-byte address (a23-a0) or ? 02h (extadd=1) is followed by a 4-byte address (a31-a0) or ? 12h is followed by a 4-byte address (a31-a0) and at least one data byte on si. depending on the device configur ation, the page size can either be 256 or 512 bytes. up to a p age can be provided on si after the 3-byte addres s with instruction 02h or 4-byte address with instruction 12h has been provided. i f the 9 least significant address bits (a8-a0) are not all 0, all transm itted data that goes beyond the end of the current page are pro grammed from the start address of the same page (f rom the address whose 9 least significant bi ts (a8-a0) are all 0) i.e. the address wr aps within the page aligned address boundaries. this is a result of only requiring the user to enter one single page address to cov er the entire page boundary. if more than a page of data is sent to the device, the data l oading sequence will wrap from the la st byte in the page to the ze ro byte location of the same page and begin overwr iting data previously loaded in the page. the last page worth of data (either 256 or 512 bytes) is programmed in the page. this is a result of the device being equipped with a page program buffer that is only page si ze in length. if less than a page of data is sent to the device, these data bytes will be programmed in sequence, starting at the pro vided address within the page, without having any affect on the ot her bytes of the same page. using the page program (pp) command to load an entire page , within the page boundary, will save overall programming time versus loading less than a page into the program buffer. the programming process is managed by the flash memory device internal control logic. after a programming command is issued, the programming operation status ca n be checked using the read status register 1 command. the wip bit (sr1[0]) will indicate when the programming operation is completed. the p_err bit (sr1[6]) will indicate if an error occurs in the programming operati on that prevents successful completion of programming. this includes attempted programming of a protected area. figure 82. page program (pp 02h or 4pp 12h) command sequence note: 1. a = msb of address = a23 for pp 02h, or a31 for 4pp 12h. cs# sck si so phase 7 65 43 2 10a 5 43 21 0 76 54 32 1 07 65 4 32 10 instruction address input data 1 input data 2 document number: 001-98282 rev. *i page 95 of 142 S25FL127S 9.5.3 quad page pr ogram (qpp 32h or 38h, or 4qpp 34h) the quad-input page program (qpp) command allo ws bytes to be programmed in the memory (changing bits from 1 to 0). the quad-input page program (qpp) command allows up to a page size (either 256 or 512 bytes) of dat a to be loaded into the page buffer using four signals: io0-io3. qpp can improve performance for prom programmer and applications that have slower clock speeds (< 12 mhz) by loading 4 bits of data per clock cycle. sy stems with faster clock speeds do not realize as much benefit fo r the qpp command since the inherent page program time becomes greater than the time it takes to clock-in the data. the maximum frequency for the qpp command is 80 mhz. to use quad page program the quad enable bit in the config uration register must be set (q uad=1). a write enable command must be executed before the devi ce will accept the qpp command (status register 1, wel=1). the instruction ? 32h (extadd=0) is followed by a 3-byte address (a23-a0) or ? 32h (extadd=1) is followed by a 4-byte address (a31-a0) or ? 38h (extadd=0) is followed by a 3-byte address (a23-a0) or ? 38h (extadd=1) is followed by a 4-byte address (a31-a0) or ? 34h is followed by a 4-byte address (a31-a0) and at least one data byte, into the io signals. data must be programmed at previously erased (ffh) memory locations. qpp requires programming to be done one full page at a time. wh ile less than a full page of data may be loaded for programming, the entire page is considered programm ed, any locations not filled with data will be left as ones, the same page must not be programmed more than once. all other functions of qpp are identical to page program. the qpp command sequence is shown in the figure below. figure 83. quad page program command sequence 9.5.4 program suspend (pgsp 85h) and resume (pgrs 8ah) the program suspend command allows the system to interrupt a programming operation and then read from any other non-erase-suspended sector or non-progra m-suspended-page. program suspend is valid only during a programming operation. commands allowed after the program suspend command is issued: ? read status register 1 (rdsr1 05h) ? read status register 2 (rdsr2 07h) the write in progress (wip) bit in status register 1 (sr1[0 ]) must be checked to know when the programming operation has stopped. the program suspend status bit in the status register 2 (sr2[0]) can be used to determine if a programming operation has been suspended or was completed at the time wip changes to 0. the time required for the suspend operation to complete is t psl , see table 42, program suspend ac parameters on page 111 . see table 40, commands allowed during program or erase suspend on page 101 for the commands allowed while programming is suspend. cs# sck io0 io1 io2 io3 phase 76543210a 104040404040 4 5151515151 5 6262626262 6 7373737373 7 instruction address data 1 data 2 data 3 data 4 data 5 ... document number: 001-98282 rev. *i page 96 of 142 S25FL127S the program resume command 8ah must be written to resume the programming operation after a program suspend. if the programming operation was completed during the suspend operation, a resume command is not needed and has no effect if issued. program resume commands will be ignored unless a program operation is suspended. after a program resume command is issued, the wip bit in the st atus register 1 will be set to a 1 and the programming operatio n will resume. program operations may be interrupted as often as necessary e.g. a program sus pend command could immediately follow a program resume command but, in order for a program oper ation to progress to completion there must be some periods of time between resume and the next suspend command greater than or equal to t prs . see table 42, program suspend ac parameters on page 111 . figure 84. program suspend command sequence figure 85. program resume command sequence program suspend instruction read status mode command prog. suspend 7 6 5 4 3 2 1 0 7 6 0 7 6 5 7 0 tpsl tpsl cs# sck si so 1 1 3 2 7 6 5 4 0 i n s t r u c t i o n ( 8 a h ) s c k s o h i g h i m p e d a n c e s i c s s # 0 1 7 6 5 4 3 2 m s b r e s u m e p r o g r a m m i n g document number: 001-98282 rev. *i page 97 of 142 S25FL127S 9.6 erase flash array commands 9.6.1 parameter 4-kb sector erase (p4e 20h or 4p4e 21h) the p4e command is implemented only in fl127s. the p4e comm and is ignored when the device is configured with the 256-kb sector option. the parameter 4-kb sector erase (p4e) command sets all the bits of a 4-kbyte parameter sector to 1 (all bytes are ffh). before the p4e command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the stat us register to enable any write operations. the instruction ? 20h [extadd=0] is followed by a 3-byte address (a23-a0), or ? 20h [extadd=1] is followed by a 4-byte address (a31-a0), or ? 21h is followed by a 4-byte address (a31-a0) cs# must be driven into the logic high st ate after the twenty-fourth or thirty-second bit of the address has been latched in on si. this will initiate the beginnin g of internal erase cycle, which in volves the pre-programming and eras e of the chosen sector of the f lash memory array. if cs# is not driven high after the last bi t of address, the sector eras e operation will not be executed. as soon as cs# is driven high, the internal erase cycle will be initiated. with the internal erase cycle in progress, the user can read the value of the write-in progress (wip) bit to determine when the operation has been completed. the wip bit will indicate a 1. when the erase cycle is in pr ogress and a 0 when the eras e cycle has been completed. a p4e command applied to a sector that has been write protected through the block protec tion bits or asp, will not be executed and will set the e_err status. a p4e command applied to a sector that is larger than 4 kbytes will not be executed and will not set the e_err status. figure 86. parameter sector erase (p4e 20h or 4p4e 21h) command sequence note: 1. a = msb of address = a23 for p4e 20h with extadd = 0, or a31 for p4e 20h with extadd = 1 or 4p4e 21h. cs# sck si so phase 76543210a 10 instruction address document number: 001-98282 rev. *i page 98 of 142 S25FL127S 9.6.2 sector erase ( se d8h or 4se dch) the sector erase (se) command sets all bits in the addressed se ctor to 1 (all bytes are ffh). before the sector erase (se) command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the instruction ? d8h [extadd=0] is followed by a 3-byte address (a23-a0), or ? d8h [extadd=1] is followed by a 4-byte address (a31-a0), or ? dch is followed by a 4-byte address (a31-a0) cs# must be driven into the logic high stat e after the twenty-fourth or thirty-second bit of address has been latched in on si. this will initiate the erase cycle, which in volves the pre-programm ing and erase of the chosen sector . if cs# is not driven high after th e last bit of address, the sector erase operation will not be executed. as soon as cs# is driven into the logic high state, the internal erase cycle will be in itiated. with the internal erase cycle i n progress, the user can read the value of the write- in progress (wip) bit to check if the operation has been completed. the wip bit will i ndicate a 1 when the erase cycle is in progress and a 0 when the erase cycle has been completed. a sector erase (se) command applied to a se ctor that has been write prot ected through the block prot ection bits or asp, will no t be executed and will set the e_err status. a device configuration determines whether th e se command erases 64 kbytes or 256 kbytes. the option to use this command to always erase 256 kbytes provides for software compatibilit y with higher density and future s25fl family devices. asp has a ppb and a dyb protection bit for eac h sector, including any 4-kb sectors. if a sector erase command is applied to a 64-kb range that includes a protected 4-kb sector, or to a 256 -kb range that includes a 64-kb protected addre ss range, the eras e will not be executed on the range and will set the e_err status. figure 87. sector erase (se d8h or 4se dch) command sequence note: 1. a = msb of address = a23 for se d8h with extadd = 0, or a31 for se d8h with extadd = 1 or 4p4e dch. cs# sck si so phase 76543210a 10 instruction address document number: 001-98282 rev. *i page 99 of 142 S25FL127S 9.6.3 bulk erase (be 60h or c7h) the bulk erase (be) command sets all bits to 1 (all bytes are ff h) inside the entire flash memory array. before the be command can be accepted by the device, a write enable (wren) command must be issued an d decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. cs# must be driven into the logic high state after the eighth bi t of the instruction byte has been latched in on si. this will initiate the erase cycle, which involves the pre-programming and erase of the entire flash memory array. if cs# is not driven high after the last bit of instruction, the be ope ration will not be executed. as soon as cs# is driven into the logic high state, the erase cycle will be initiate d. with the erase cycle in progress, the us er can read the value of the write-in progress (wip) bit to determine when the operation has been completed. the wip bit will indicate a 1 when the erase cycle is in pr ogress and a 0 when the eras e cycle has been completed. a be command can be executed only when the block protection (bp2, bp1, bp0) bits are set to 0?s. if the bp bits are not 0, the be command is not executed and e_err is not set. the be comma nd will skip any sectors protected by the dyb or ppb and the e_err status will not be set. figure 88. bulk erase command sequence 9.6.4 erase suspend and resume co mmands (ersp 75h or errs 7ah) the erase suspend command, allows the system to interrupt a sect or erase operation and then read from or program data to, any other sector. erase suspend is valid only during a sector erase operation. the erase suspend comma nd is ignored if written duri ng the bulk erase operation. when the erase suspend command is writ ten during the sector erase operation, the device requires a maximum of t esl (erase suspend latency) to suspend the erase ope ration and update the status bits. see table 43, erase suspend ac parameters on page 111 . commands allowed after the erase suspend command is issued: ? read status register 1 (rdsr1 05h) ? read status register 2 (rdsr2 07h) the write in progress (wip) bit in status register 1 (sr1[0]) must be checked to know when the erase operation has stopped. the erase suspend bit in status register 2 (sr2[1]) can be used to determine if an erase operation has been suspended or was completed at the time wip changes to 0. if the erase operation was completed during t he suspend operation, a resume command is not needed and has no effect if issued. erase resume commands will be ignored unless an erase operation is suspended. see table 40, commands allowed during program or erase suspend on page 101 for the commands allowed while erase is suspend. after the erase operation has been suspended, the sector enters the erase-suspend mo de. the system can read data from or program data to the device. reading at any address within an erase-suspended sector produces undetermined data. a wren command is required before any command that will change non-volatile data, even during erase suspend. 3 27 6 5 4 0 instruction sck si 1 cs# document number: 001-98282 rev. *i page 100 of 142 S25FL127S the wrr and ppb erase commands are not allowed during erase suspe nd, it is therefore not possibl e to alter the block protection or ppb bits during erase suspend. if there are sectors that may need programming duri ng erase suspend, these sectors should be protected only by dyb bits that can be turned off during erase su spend. however, wrr is allowed immediately following the brac command; in this special case the wrr is interpreted as a wr ite to the bank address register, not a write to sr1 or cr1. if a program command is sent for a location within an erase susp ended sector the program operation will fail with the p_err bit set. after an erase-suspended program operation is complete, the device returns to the erase-suspend mode. the system can determine the status of the program operati on by reading the wip bit in the status r egister, just as in the standard program operation. the erase resume command 7ah must be written to resume th e erase operation if an erase is suspended. erase resume commands will be ignored unless an erase is suspended. after an erase resume command is sent, the wip bit in the status register will be se t to a 1 and the erase operation will conti nue. further resume commands are ignored. erase operations may be interrupted as often as necessary e.g. an erase suspend command could immediately follow an erase resume command but, in order for an erase operation to progress to completion there must be some periods of time between resume and the next suspend command greater than or equal to t ers . see table 43, erase suspend ac parameters on page 111 . figure 89. erase suspend command sequence figure 90. erase resume command sequence erase suspend instruction read status mode command erase suspend 7 6 5 4 3 2 1 0 7 6 0 7 6 5 7 0 tesl tesl cs# sclk si so 1 1 3 2 7 6 5 4 0 i n s t r u c t i o n ( 7 a h ) s c k s o h i g h i m p e d a n c e s i c s s # 0 1 7 6 5 4 3 2 m s b r e s u m e s e c t o r o r b l o c k e r a s e document number: 001-98282 rev. *i page 101 of 142 S25FL127S table 40. commands allowed during program or erase suspend instruction name instruction code (hex) allowed during erase suspend allowed during program suspend comment brac b9 x x bank address register may need to be changed during a suspend to reach a sector for read or program. brrd 16 x x bank address register may need to be changed during a suspend to reach a sector for read or program. brwr 17 x x bank address register may need to be changed during a suspend to reach a sector for read or program. clsr 30 x clear status may be used if a pr ogram operation fails during erase suspend. dybrd e0 x it may be necessary to remove and restore dynamic protection during erase suspend to allow programming during erase suspend. dybwr e1 x it may be necessary to remove and restore dynamic protection during erase suspend to allow programming during erase suspend. errs 7a x required to resume from erase suspend. fast_read 0b x x all array reads allowed in suspend. 4fast_read 0c x x all array reads allowed in suspend. mbr ff x x may need to reset a read operation during suspend. pgrs 8a x x needed to resume a program operation. a program resume may also be used during nested program suspend within an erase suspend. pgsp 85 x program suspend allowed during erase suspend. pp 02 x required for array program during erase suspend. 4pp 12 x required for array program during erase suspend. ppbrd e2 x allowed for checking persistent protection before attempting a program command during erase suspend. qpp 32, 38 x required for array program during erase suspend. 4qpp 34 x required for array program during erase suspend. 4read 13 x x all array reads allowed in suspend. rdcr 35 x x dior bb x x all array reads allowed in suspend. 4dior bc x x all array reads allowed in suspend. dor 3b x x all array reads allowed in suspend. 4dor 3c x x all array reads allowed in suspend. qior eb x x all array reads allowed in suspend. 4qior ec x x all array reads allowed in suspend. qor 6b x x all array reads allowed in suspend. 4qor 6c x x all array reads allowed in suspend. rdsr1 05 x x needed to read wip to determine end of suspend process. rdsr2 07 x x needed to read suspend status to determine whether the operation is suspended or complete. read 03 x x all array reads allowed in suspend. reset f0 x x reset allowed anytime. wren 06 x required for program command within erase suspend. wrr 01 x x bank register may need to be changed during a suspend to reach a sector needed for read or program. wrr is allowed when following brac. document number: 001-98282 rev. *i page 102 of 142 S25FL127S 9.7 one time program array commands 9.7.1 otp program (otpp 42h) the otp program command programs data in the one time program region, which is in a different address space from the main array data. the otp region is 1024 bytes so, the address bits from a23 to a10 must be 0 for this command. refer to section 7.5 otp address space on page 49 for details on the otp region. the protocol of the otp program command is the same as the page program command. before the otp program command can be accept ed by the device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latc h (wel) in the status register to enable any write operations . the wip bit in sr1 may be checked to determine when the operation is completed. the p_err bit in sr1 may be checked to determine if any error occurred during the operation. to program the otp array in bit granularity, the rest of the bits within a data byte can be set to 1. each region in the otp memory space can be programmed one or more times, provided that the region is not locked. attempting to program 0s in a region that is locked will fail with the p_err bi t in sr1 set to 1 programming ones, even in a protected area d oes not cause an error and does not set p_err. subsequent otp prog ramming can be performed only on the un-programmed bits (that is, 1 data). figure 91. otp program command sequence 9.7.2 otp read (otpr 4bh) the otp read command reads data from the otp region. the otp regi on is 1024 bytes so, the address bits from a23 to a10 must be 0 for this co mmand. refer to otp address space on page 49 for details on the otp region. the protocol of the otp read command is similar to the fast read command except that it will not wrap to the starting address after the otp address is at it s maximum; instead, the data beyond the maxi mum otp address will be undefined. also, the otp read command is not affected by the latency code. the otp read command always has one dummy byte of latency as shown below. figure 92. otp read command sequence 13 210 9 8 7 6 5 4 031 30 29 2 8 instructio n 24-bit addres s 23 21 22 1 32 0 36 35 34 33 32 39 38 3 7 1 32 0 765 4 data byte 1 4 12 0 1 32 0 765 4 data byte 2 44 43 42 41 40 47 46 4 552 51 59 49 48 55 54 5 3 1 32 0 765 4 data byte 3 4127 4126 4 125 4124 4 1 2 3 4122 412 1 data byte 51 2 sck si sck si msb msb msb msb msb cs# c s# 1 32 0 765 4 1 32 0 76 54 1 3 2 1 0 9 8 7 6 5 4 0 3 1 3 0 2 9 2 8 i n s t r u c t i o n 2 4 - b i t a d d r e s s 2 3 2 1 2 2 1 3 2 0 1 3 2 0 7 6 5 4 3 6 3 5 3 4 3 3 3 2 3 9 3 8 3 7 1 3 2 0 7 6 5 4 d u m m y b y t e 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 d a t a o u t 1 d a t a o u t 2 s c k s i s o m s b h i g h i m p e d a n c e 7 m s b c s s # document number: 001-98282 rev. *i page 103 of 142 S25FL127S 9.8 advanced sector protection commands 9.8.1 asp read (asprd 2bh) the asp read instruction 2bh is shifted into si by the rising edg e of the sck signal. then the 16-bit asp regist er contents are shifted out on the serial output so, least significant byte firs t. each bit is shifted out at the sck frequency by the falling edge of the sck signal. it is possible to read the asp re gister continuously by prov iding multiples of 16 clo ck cycles. the maximum operati ng clock frequency for the asp read (asprd) command is 108 mhz. figure 93. asprd command 9.8.2 asp program (aspp 2fh) before the asp program (aspp) command can be accepted by the dev ice, a write enable (wren) command must be issued. after the write enable (wren) command has been decoded, the device will set the write enable latch (wel) in the status register to enable any write operations. the aspp command is entered by driv ing cs# to the logic low state, followed by the instruction and two data bytes on si, least significant byte first. the asp regist er is two data bytes in length. the aspp command affects the p_err and wip bits of the status and configuration registers in the same manner as any other programming operation. cs# input must be driven to the logic high state after the sixteenth bit of data has been latched in. if not, the aspp command is not executed. as soon as cs# is driven to the logic high state, the self-timed aspp operation is initiated. while the aspp operatio n is in progress, the status register may be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bi t is a 1 during the self-timed aspp operation, and is a 0 when it is completed. when the aspp operation is complet ed, the write enable latch (wel) is set to a 0. figure 94. aspp command 1 3 2 10 9 8 7 6 5 4 0 14 13 12 11 instruction 1 3 2 0 7 6 5 4 sck so high impedance msb register out si 15 18 17 16 22 21 20 19 9 11 10 8 15 14 13 12 msb register out 23 7 msb cs# 0 1 7 6 5 4 3 2 msb instruction register in 1 3 2 10 9 8 7 6 5 4 0 14 13 12 11 15 1 3 2 0 7 6 5 4 sck si so msb high impedance cs# 0 1 7 6 5 4 3 2 msb 18 17 16 22 21 20 19 23 9 11 10 8 15 14 13 12 document number: 001-98282 rev. *i page 104 of 142 S25FL127S 9.8.3 dyb read (dybrd e0h) the instruction e0h is latched into si by the rising edge of the sck signal. the inst ruction is followed by the 32-bit address selecting location zero within the desired sector note: the high order addre ss bits not used by a particular density device must be 0. th en the 8-bit dyb access register contents are shifted out on the serial output so. each bit is shifted out at the sck frequency by the falling edge of the sck signal. it is possible to read the same dyb acce ss register continuously by prov iding multiples of eight clock cycles. the address of the dyb register does not increment so this is not a means to read the entire dyb array. each location must be r ead with a separate dyb read command. the maximum operating clock frequency for read command is 108 mhz. figure 95. dybrd command sequence 9.8.4 dyb write (dybwr e1h) before the dyb write (dybwr) command can be accepted by the dev ice, a write enable (wren) command must be issued. after the write enable (wren) command has been decoded, the device will set the write enable latch (wel) in the status register to enable any write operations. the dybwr command is entered by driving cs# to the logic low st ate, followed by the instruction, the 32-bit address selecting location zero within the desired sector (note, the high order a ddress bits not used by a particular density device must be 0), then the data byte on si. the dyb access register is one data byte in length. the dybwr command affects the p_err and wip bits of the status and configuration re gisters in the same manner as any other programming operation. cs# must be driven to the logic high state after the eighth bit of data has been latc hed in. if not, the dybwr command is not executed. as soon as cs# is driven to the logic high state, the self-timed dybwr operation is initiated. while t he dybwr operation is in progress, the status register may be read to check the value of the write-in progress (wip) bit. the writ e-in progress (wip) bit is a 1 during the self-tim ed dybwr operation, and is a 0 when it is completed. when the dybwr operation is completed, the write enable latch (wel) is set to a 0. figure 96. dybwr command sequence 1 3 210 9 8 7 6 5 4 039 38 37 36 instruction 32-bit address 31 29 30 1 32 0 1 32 0 7654 44 43 42 41 40 47 46 45 data out 1 sck si so msb high impedance cs# 1 32 0 7654 13 210 9 8 7 6 5 4 039 38 37 3 6 instructio n 32-bit addres s 31 29 30 1 32 0 44 43 42 41 40 47 46 4 5 1 32 0 76 5 4 data byte 1 sck si msb msb c s# 1 32 0 7654 document number: 001-98282 rev. *i page 105 of 142 S25FL127S 9.8.5 ppb read (ppbrd e2h) the instruction e2h is shifted into si by the rising edges of the sck signal, followed by the 32-bit address selecting location zero within the desired sector. note: the high order address bits not us ed by a particular density device must be 0. then the 8-bit ppb access register contents are shifted out on so. it is possible to read the same ppb access re gister continuously by providing multiple s of eight clock cycles. the address of t he ppb register does not increment so this is not a means to read the entire ppb array. each location must be read with a separate ppb read command. the maximum operating clock frequency for the ppb read command is 108 mhz. figure 97. ppbrd command sequence 9.8.6 ppb program (ppbp e3h) before the ppb program (ppbp) command can be accepted by the dev ice, a write enable (wren) command must be issued. after the write enable (wren) command has been decoded, the device will set the write enable latch (wel) in the status register to enable any write operations. the ppbp command is entered by dr iving cs# to the lo gic low state, followed by the instru ction, followed by the 32-bit address selecting location zero within the desired sector (note, the high order address bits not used by a particular density device mu st be 0). the ppbp command affects the p_err and wip bits of the status and configuration registers in the same manner as any other programming operation. cs# must be driven to the logic high stat e after the last bit of address has been latched in. if not, the ppbp command is not executed. as soon as cs# is driven to the logic high state, the self-timed ppbp operation is initiated. while the ppbp operatio n is in progress, the status register may be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bi t is a 1 during the self-timed ppbp operation, and is a 0 when it is completed. when the ppbp operation is complet ed, the write enable latch (wel) is set to a 0. figure 98. ppbp command sequence 1 3 210 9 8 7 6 5 4 039 38 37 36 instruction 32-bit address 31 29 30 1 32 0 1 32 0 7654 44 43 42 41 40 47 46 45 data out 1 sck si so msb high impedance cs# 765 4321 0 i i n s t r u c t i o n 3 2 b i t a d d r e s s 1 3 2 1 0 9 8 7 6 5 4 0 3 8 3 7 3 6 3 9 0 1 3 1 3 0 2 9 3 2 s c k s i s o m s b h i g h i m p e d a n c e c s s # 0 1 7 6 5 4 3 2 m s b 3 5 document number: 001-98282 rev. *i page 106 of 142 S25FL127S 9.8.7 ppb erase (ppbe e4h) the ppb erase (ppbe) command sets all ppb bits to 1. before the ppb erase command can be ac cepted by the device, a write enable (wren) command must be issued and decoded by the devi ce, which sets the write enable latch (wel) in the status register to enable any write operations. the instruction e4h is shifted into si by the rising edges of the sck signal. cs# must be driven into the logic high state after the eighth bi t of the instruction byte has been latched in on si. this will initiate the beginning of internal erase cycl e, which involves the pre-prog ramming and erase of the entire ppb memory array. without cs# being driven to the logic high state after the eighth bit of the instruction, the ppb eras e operation will not be executed. with the internal erase cycle in progress, the user can read th e value of the write- in progress (wip) bit to check if the opera tion has been completed. the wip bit will indicate a 1 when the erase cycle is in progress and a 0 when the erase cycle has been complet ed. erase suspend is not allowed during ppb erase. figure 99. ppb erase command sequence 9.8.8 ppb lock bit read (plbrd a7h) the ppb lock bit read (plbrd) command allows the ppb lock register contents to be read out of so. it is possible to read the ppb lock register continuously by providing multiples of eight clock cycles. the ppb lo ck register contents may only be read wh en the device is in standby state with no other operation in progress. it is recommended to check the write-in progress (wip) bit of the status register before issui ng a new command to the device. figure 100. ppb lock register read command sequence 1 3 27 6 5 4 0 instructio n sck so high impedance s i cs# 0 1 7 6 5 4 3 2 ms b cs# sck si so phase 76543210 7654321076543210 instruction register read repeat register read document number: 001-98282 rev. *i page 107 of 142 S25FL127S 9.8.9 ppb lock bit write (plbwr a6h) the ppb lock bit write (plbwr) co mmand clears the ppb lock register to 0. be fore the plbwr comman d can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the plbwr command is entered by driving cs# to the logic low state, followed by the instruction. cs# must be driven to the logic high state after the eighth bit of instruction has b een latched in. if not, the plbwr command i s not executed. as soon as cs# is dr iven to the logic high state, th e self-timed plbwr operation is initiated. while the plbwr operat ion is in progress, the status register may st ill be read to check the value of the writ e-in progress (wip) bit. the write-in progr ess (wip) bit is a 1 during the self-timed plbwr op eration, and is a 0 when it is complete d. when the plbwr o peration is completed, the write enable latch (wel) is set to a 0. the maximum clock frequency for the plbwr command is 108 mhz. figure 101. ppb lock bit write command sequence 9.8.10 password r ead (passrd e7h) the correct password value may be read only after it is pr ogrammed and before the password mode has been selected by programming the password protection mode bi t to 0 in the asp register (a sp[2]). after the password pr otection mode is selected the passrd command is ignored. the passrd command is shifted into si. then th e 64-bit password is shifted out on the serial output so, least significant byte first, most significant bit of each byte first. each bit is shifted out at the sck frequency by the falling edge of the sck signal. it is possible to read the password continuously by pr oviding multiples of 64 cloc k cycles. the maximum operati ng clock frequency for the passrd command is 108 mhz. figure 102. password read command sequence 1 3 27 6 5 4 0 instruction sck so high impedance si cs# 0 1 7 6 5 4 3 2 msb 7 56 57 6 5 4 5 8 13 210 9 8 7 6 5 4 0 70 69 1 1 instructio n sck so high impedance msb password least sig. byte first s i 7 1 72 ms b 7 cs# 0 1 7 6 5 4 3 2 ms b document number: 001-98282 rev. *i page 108 of 142 S25FL127S 9.8.11 password pr ogram (passp e8h) before the password program (passp) comma nd can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) command has been decoded, the device sets the write enable latch (wel) to enabl e the passp operation. the password can only be programmed before the password mode is selected by programming th e password protection mode bit to 0 in the asp register (asp[2]). af ter the password protection mode is se lected the passp command is ignored. the passp command is entered by driving cs# to the logic low stat e, followed by the instruction and the password data bytes on si, least significant byte first, most signi ficant bit of each byte first. the passwo rd is sixty-four (64) bits in length. cs# must be driven to the logic high state after the sixty-fourth (64 th ) bit of data has been latched. if no t, the passp command is not executed. as soon as cs# is driven to the logic high state, the se lf-timed passp operation is init iated. while the passp operat ion is in progress, the status register may be read to check the va lue of the write-in progress (wip ) bit. the write-in progress (w ip) bit is a 1 during the self-timed passp cycle, and is a 0 when it is complet ed. the passp command can repo rt a program error in the p_err bit of the status register. when the passp operation is co mpleted, the write enable latch (wel) is set to a 0. the maximum clock frequency for the passp command is 108 mhz. figure 103. password program command sequence 9.8.12 password unlock (passu e9h) the passu command is entered by driving cs# to the logic low st ate, followed by the instruction and the pa ssword data bytes on si, least significant byte first, most signi ficant bit of each byte first. the passwo rd is sixty-four (64) bits in length. cs# must be driven to the logic high state after the sixty-fourth (64 th ) bit of data has been latched. if not, the passu command is not executed. as soon as cs# is driven to the logic high state, the self-timed passu oper ation is initiated. while the passu operat ion is in progress, the status register may be read to check the va lue of the write-in progress (wip ) bit. the write-in progress (w ip) bit is a 1 during the self-timed passu cycle, and is a 0 when it is completed. if the passu command supplied password does not match the hidden password in the password register, an error is reported by setting the p_err bit to 1. the wip bit of the status register al so remains set to 1. it is necessary to use the clsr command t o clear the status register, the reset comman d to software reset the device, or drive th e reset# input low to initiate a hardware reset, in order to return the p_err and wip bits to 0. this returns the device to standby state, ready for new commands such as a retry of the passu command. if the password does match, the ppb lock bi t is set to 1. the maximum clock fr equency for the passu command is 108 mhz. instruction password 1 3 210 9 8 7 6 5 4 0 70 69 68 71 56 57 7 6 5 59 58 sck si so msb high impedance cs# 0 1 7 6 5 4 3 2 msb document number: 001-98282 rev. *i page 109 of 142 S25FL127S figure 104. password unlock command sequence 9.9 reset commands 9.9.1 software reset command (reset f0h) the software reset command (reset) restores th e device to its init ial power up state, except for the volatile freeze bit in the configuration register cr1[1] and the volatile ppb lock bit in the ppb lock register. the freeze bit and the ppb lock bit will remain set at their last value prior to t he software reset. to clear the freeze bit and set the ppb lock bit to its protection mode selected power on state, a full power-on-reset sequence or hardware reset must be done. note that the non-volatile bits in the configuration register, tbprot, tbparm, and bpnv, retain their pr evious state after a software reset. the block protection bits bp2, bp1, and bp0, in the status register w ill only be reset if they are configured as volatile via the bpnv bit in the configu ration register (cr1[3]) and freeze is cleared to 0. the software re set cannot be used to circumv ent the freeze or ppb lock bit protection mechanisms for the other security configuration bits. the reset command is executed when cs# is brought to high stat e and requires t rph time to execute. figure 105. software reset command sequence instruction password 1 3 210 9 8 7 6 5 4 0 70 69 68 71 56 57 7 6 5 59 58 sck si so msb high impedance cs# 0 1 7 6 5 4 3 2 msb 3 27 6 5 4 0 instructio n sck s i 1 cs# document number: 001-98282 rev. *i page 110 of 142 S25FL127S 9.9.2 mode bit reset (mbr ffh) the mode bit reset (mbr) command can be used to return the device from continuous high performance read mode back to normal standby awaiting any new command. becaus e some device packages la ck a hardware reset# input a nd a device that is in a continuous high performance read mode may not recognize any norma l spi command, a system hardwa re reset or so ftware reset command may not be recognized by the device. it is recomme nded to use the mbr command after a system reset when the reset# signal is not available or, before sending a software rese t, to ensure the device is released from continuous high performance read mode. the mbr command sends ones on si or io0 for 8 sck cycles. io1 to io 3 are ?don?t care? during these cycles. figure 106. mode bit reset command sequence 9.10 embedded algorithm performance tables the joint electron device engineering council (jedec) standard j esd22-a117 defines the procedural requirements for performing valid endurance and retention tests based on a qualification specification. this methodology is intended to determine the abili ty of a flash device to sustain repeated data changes without failure (progr am/erase endurance) and to retain data for the expected lif e (data retention). endurance and retention qualification specif ications are specified in jesd47 or may be developed using knowledge-based methods as in jesd94. notes: 1. typical program and erase times assume the following conditions: 25c, v cc = 3.0v; random data pattern. 2. under worst case conditions of 90c; 100,000 cycles max. 3. the programming time for any otp programming command is the same as t pp . this includes otpp 42h, pnvdlr 43h, aspp 2fh, and passp e8h. the programming time for the ppbp e3h command is the same as t pp . 4. the erase time for ppbe e4h command is the same as t se . 5. data retention of 20 years is based on 1k erase cycles or less. table 41. program and erase performance symbol parameter min typ (1) max (2) unit t w wrr write time 130 780 ms t pp page programming (512 bytes) page programming (256 bytes) 640 395 1480 1185 (3) s t se sector erase time (64-kb / 4- kb physical sectors) 130 780 (4) ms sector erase time (64 kb top/bottom: logical sector = 16 x 4-kb physical sectors) 2,100 12,600 ms sector erase time (256-kb logical sectors = 4 x 64-kb physical sectors) 520 3120 ms t be bulk erase time (hybrid 4 kb top/ bottom with 64-kb uniform) 35 210 sec bulk erase time (256-kb uniform) 33 200 sec erase per sector 100,000 cycles 1 1 3 2 7 6 5 4 0 i n s t r u c t i o n ( f f h ) s c k s o h i g h i m p e d a n c e s i c s s # document number: 001-98282 rev. *i page 111 of 142 S25FL127S table 42. program suspend ac parameters parameter min typical max unit comments program suspend latency (t psl ) 45 s the time from program suspend command until the wip bit is 0 program resume to next program suspend (t prs ) 0.06 100 s minimum is the time needed to issue the next program suspend command but typical periods are needed for program to progress to completion table 43. erase suspend ac parameters parameter min typical max unit comments erase suspend latency (t esl ) 45 s the time from erase suspend command until the wip bit is 0 erase resume to next erase suspend (t ers) 0.06 100 s minimum is the time needed to issue the next erase suspend command but typical periods are needed for the erase to progress to completion document number: 001-98282 rev. *i page 112 of 142 S25FL127S 10. data integrity 10.1 erase endurance note: 1. each write command to a non-volatile register causes a pe cycl e on the entire non-volatile register array. otp bits and regis ters internally reside in a separate array that is not pe cycled. 10.2 data retention contact cypress sales and fae for further information on th e data integrity. an application note is available at: www.cypress.com/appnotes . table 10.1 erase endurance parameter minimum unit program/erase cycles per main flash array sectors 100k pe cycle program/erase cycles per ppb array or non-volatile register array (1) 100k pe cycle table 10.2 data retention parameter test conditions minimum time unit data retention time 10k program/erase cycles 20 years 100k program/erase cycles 2 years document number: 001-98282 rev. *i page 113 of 142 S25FL127S 11. software interface reference 11.1 command summary table 44. fl127s command set (sorted by instruction) instruction (hex) command name command description maximum frequency (mhz) 01 wrr write register (status-1, configuration-1) 108 02 pp page program (3- or 4-byte address) 108 03 read read (3- or 4-byte address) 50 04 wrdi write disable 108 05 rdsr1 read status register 1 108 06 wren write enable 108 07 rdsr2 read status register 2 108 0b fast_read fast read (3- or 4-byte address) 108 0c 4fast_read fast read (4-byte address) 108 12 4pp page program (4-byte address) 108 13 4read read (4-byte address) 50 14 abrd autoboot register read 108 15 abwr autoboot register write 108 16 brrd bank register read 108 17 brwr bank register write 108 18 eccrd ecc read 108 20 p4e parameter 4 kb-sector erase (3- or 4-byte address) 108 21 4p4e parameter 4 kb-sector erase (4-byte address) 108 2b asprd asp read 108 2f aspp asp program 108 30 clsr clear status register - erase/program fail reset 108 32 qpp quad page program (3- or 4-byte address) 80 34 4qpp quad page program (4-byte address) 80 35 rdcr read configuration register 1 108 38 qpp quad page program (3- or 4-byte address) 80 3b dor read dual out (3- or 4-byte address) 108 3c 4dor read dual out (4-byte address) 108 42 otpp otp program 108 4b otpr otp read 108 5a rsfdp read jedec serial flash discoverable parameters 108 60 be bulk erase 108 6b qor read quad out (3- or 4-byte address) 108 6c 4qor read quad out (4-byte address) 108 75 ersp erase suspend 108 7a errs erase resume 108 85 pgsp program suspend 108 8a pgrs program resume 108 90 read_id (rems) read electronic manufacturer signature 108 9f rdid read id (jedec manufacturer id and jedec cfi) 108 a3 reserved-a3 reserved 108 a6 plbwr ppb lock bit write 108 document number: 001-98282 rev. *i page 114 of 142 S25FL127S a7 plbrd ppb lock bit read 108 ab res read electronic signature 50 b9 brac bank register access (legacy command formerly used for deep power down) 108 bb dior dual i/o read (3- or 4-byte address) 108 bc 4dior dual i/o read (4-byte address) 108 c7 be bulk erase (alternate command) 108 d8 se erase 64 kb or 256 kb (3- or 4-byte address) 108 dc 4se erase 64 kb or 256 kb (4-byte address) 108 e0 dybrd dyb read 108 e1 dybwr dyb write 108 e2 ppbrd ppb read 108 e3 ppbp ppb program 108 e4 ppbe ppb erase 108 e5 reserved-e5 reserved e6 reserved-e6 reserved e7 passrd password read 108 e8 passp password program 108 e9 passu password unlock 108 eb qior quad i/o read (3- or 4-byte address) 108 ec 4qior quad i/o read (4-byte address) 108 f0 reset software reset 108 ff mbr mode bit reset 108 table 44. fl127s command set (sorted by instruction) (continued) instruction (hex) command name command description maximum frequency (mhz) document number: 001-98282 rev. *i page 115 of 142 S25FL127S 12. serial flash discoverable pa rameters (sfdp) address map the sfdp address space has a header starting at address 0 that id entifies the sfdp data structure and provides a pointer to eac h parameter. one basic flash parameter is mandated by the jedec jesd216b standard. tw o optional parameter tables for sector map and 4-byte address instructions follow the basic flash table. cypress provides an additional parameter by pointing to the id-cfi address space i.e. the idcfi address space is a sub-set of the sfdp address space. the parameter tables portion of the sfdp data structure are located within the id-cfi address space and is thus both a cfi parameter and an sfdp parameter. in this way both sfdp and id-cfi information can be accessed by either the rsfdp or rdid commands. table 45. sfdp overview map byte address description 0000h location zero within jedec jesd216b sfdp space ? start of sfdp header ,,, remainder of sfdp header followed by undefined space 1000h location zero within id-cfi space ? start of id-cfi parameter tables ... id-cfi parameters 1120h start of sfdp parameter which is one of the cfi parameter tables ... remainder of sfdp parameter tables followed by either more cfi parameters or undefined space document number: 001-98282 rev. *i page 116 of 142 S25FL127S 12.1 sfdp header field definitions table 46. sfdp header sfdp byte address sfdp dword name data description 00h sfdp header 1st dword 53h this is the entry point for read sfdp (5ah) command i.e. location zero within sfdp space ascii ?s? 01h 46h ascii ?f? 02h 44h ascii ?d? 03h 50h ascii ?p? 04h sfdp header 2nd dword 06h sfdp minor revision (06h = jedec jesd216 revision b) this re vision is backward compatible with all prior minor revisions. minor revisions are changes that define previously reserved fields, add fields to the end, or that clar ify definitions of existing fields. increments of the minor revision value indicate that previously reserved parameter fields may have been assigned a new definition or entire dwords may have been added to the parameter table. however, the definition of previously exis ting fields is unchanged and therefore remain backward compatible with earlier sfdp parameter table revisions. software can safely ignore increments of the minor revision number, as long as only those parameters the software was designed to support are used i.e. previously reserved fields and additional dwords must be masked or ignored. do not do a simple compare on the minor revision number, looking only for a match with the revision number that the software is designed to handle. there is no problem with using a higher number minor revision. 05h 01h sfdp major revision. this is the original major revision. this major revision is compatible with all sfdp reading and parsing software. 06h 05h number of parameter headers (zero based, 05h = 6 parameters) 07h ffh unused 08h parameter header 0 1st dword 00h parameter id lsb (00h = jedec sfdp basic spi flash parameter) 09h 00h parameter minor revision (00h = jesd216) - this older revision parameter header is provided for any legacy sfdp reading and parsing software that requires seeing a minor revision 0 parameter header. sfdp software designed to handle later minor revisions should continue reading parameter headers looking for a higher numbered minor revision that contains additional parameters for that software revision. 0ah 01h parameter major revision (01h = the original major revision - all sfdp software is compatible with this major revision. 0bh 09h parameter table length (in double words = dwords = 4 byte units) 09h = 9 dwords 0ch parameter header 0 2nd dword 20h parameter table pointer byte 0 (dword = 4 byte aligned) jedec basic spi flash parameter byte offset = 1120h 0dh 11h parameter table pointer byte 1 0eh 00h parameter table pointer byte 2 0fh ffh parameter id msb (ffh = jedec defined legacy parameter id) 10h parameter header 1 1st dword 00h parameter id lsb (00h = jedec sfdp basic spi flash parameter) 11h 05h parameter minor revision (05h = jesd216 revision a) - this older revision parameter header is provided for any legacy sfdp reading and parsing software that requires seeing a minor revision 5 parameter header. sfdp software designed to handle later minor revisions should continue reading parameter headers lookin g for a later minor revision that contains additional parameters. 12h 01h parameter major revision (01h = the original major revision - all sfdp software is compatible with this major revision. 13h 10h parameter table length (in double words = dwords = 4 byte units) 10h = 16 dwords 14h parameter header 1 2nd dword 20h parameter table pointer byte 0 (dword = 4 byte aligned) jedec basic spi flash parameter byte offset = 1120h address 15h 11h parameter table pointer byte 1 16h 00h parameter table pointer byte 2 17h ffh parameter id msb (ffh = jedec defined parameter) document number: 001-98282 rev. *i page 117 of 142 S25FL127S 18h parameter header 2 1st dword 00h parameter id lsb (00h = jedec sfdp basic spi flash parameter) 19h 06h parameter minor revision (06h = jesd216 revision b) 1ah 01h parameter major revision (01h = the original major revision - all sfdp software is compatible with this major revision. 1bh 10h parameter table length (in double words = dwords = 4 byte units) 10h = 16 dwords 1ch parameter header 2 2nd dword 20h parameter table pointer byte 0 (dword = 4 byte aligned) jedec basic spi flash parameter byte offset = 1120h address 1dh 11h parameter table pointer byte 1 1eh 00h parameter table pointer byte 2 1fh ffh parameter id msb (ffh = jedec defined parameter) 20h parameter header 3 1st dword 81h parameter id lsb (81h = sfdp sector map parameter) 21h 00h parameter minor revision (00h = init ial version as defined in jesd216 revision b) 22h 01h parameter major revision (01h = the original major revision - all sfdp software that recognizes this parameter?s id is compatible with this major revision. 23h 0eh parameter table length (in double words = dwords = 4 byte units) 0eh = 14 dwords 24h parameter header 3 2nd dword 60h parameter table pointer byte 0 (dword = 4 byte aligned) jedec parameter byte offset = 1160h 25h 11h parameter table pointer byte 1 26h 00h parameter table pointer byte 2 27h ffh parameter id msb (ffh = jedec defined parameter) 28h parameter header 4 1st dword 84h parameter id lsb (00h = sfdp 4 byte address instructions parameter) 29h 00h parameter minor revision (00h = init ial version as defined in jesd216 revision b) 2ah 01h parameter major revision (01h = the original major revision - all sfdp software that recognizes this parameter?s id is compatible with this major revision. 2bh 02h parameter table length (in double words = dwords = 4 byte units) (2h = 2 dwords) 2ch parameter header 4 2nd dword 98h parameter table pointer byte 0 (dword = 4 byte aligned) jedec parameter byte offset = 1198h 2dh 11h parameter table pointer byte 1 2eh 00h parameter table pointer byte 2 2fh ffh parameter id msb (ffh = jedec defined parameter) 30h parameter header 5 1st dword 01h parameter id lsb (cypress vendor specific id-cfi parameter) legacy manufacturer id 01h = amd / cypress 31h 01h parameter minor revision (01h = id-cfi updated with sfdp rev b table) 32h 01h parameter major revision (01h = the original major revision - all sfdp software that recognizes this parameter?s id is compatible with this major revision. 33h 68h parameter table length (in double words = dwords = 4 byte units) cfi starts at 1000h, the final sfdp parameter (cfi id = a5) starts at 111eh (sfdp starting point of 1120h -2hb of cfi parameter header), for a length of 11ehb excluding the cfi a5 parameter. the final cfi a5 parameter adds an additional 82hb for a total of 11eh + 82h = 1a0hb. 1a0hb/4 = 68h dwords 34h parameter header 5 2nd dword 00h parameter table pointer byte 0 (dword = 4 byte aligned) entry point for id-cfi parameter is byte offset = 1000h relative to sfdp location zero. 35h 10h parameter table pointer byte 1 36h 00h parameter table pointer byte 2 37h 01h parameter id msb (01h = jedec jep106 bank number 1) table 46. sfdp header (continued) sfdp byte address sfdp dword name data description document number: 001-98282 rev. *i page 118 of 142 S25FL127S 12.2 device id and common flash interface (id-cfi) address map 12.2.1 field definitions table 47. manufacturer and device id byte address data description 00h 01h manufacturer id for cypress 01h 20h (128 mb) device id most significant byte - memory interface type 02h 18h (128 mb) device id least significant byte - density 03h 4dh id-cfi length - number bytes following. adding this value to the current location of 03h gives the addr ess of the last valid location in the legacy id-cfi address map. this only includes up to the end of the primary vendor specif ic table. the alternate vendor specific table contains additional information. 04h 00h (uniform 256-kb sectors) 01h (4-kb parameter sectors with uniform 64-kb sectors) sector architecture 05h 80h (fl-s family) family id 06h xxh ascii characters for model refer to ordering information on page 138 for the model number definitions. 07h xxh 08h xxh reserved 09h xxh reserved 0ah xxh reserved 0bh xxh reserved 0ch xxh reserved 0dh xxh reserved 0eh xxh reserved 0fh xxh reserved table 48. cfi query identification string byte address data description 10h 11h 12h 51h 52h 59h query unique ascii string ?qry? 13h 14h 02h 00h primary oem command set fl-p backward compatible command set id 15h 16h 40h 00h address for primary extended table 17h 18h 53h 46h alternate oem command set ascii characters ?fs? for spi (f) interface, s technology 19h 1ah 51h 00h address for alternate oem extended table document number: 001-98282 rev. *i page 119 of 142 S25FL127S note: 1. fl127s 128 mbit devices have either a hybrid sector architec ture with sixteen 4 kb sectors and all remaining sectors of 64 kb or with uniform 256 kb sectors. devices with the hybrid sector architecture are initially shipped from cypress with the 4 kb sectors located at the bottom of the array address map. however, the device configuration tbparm bit cr1[2] may be programed to invert the sector map to place the 4 kb sectors at the top of the array add ress map. the cfi geometry information of the above table is relevant only to the initial delivery state of a hybrid sector device. the flash device drive r software must examine the tbparm bit to determine if the sector map was inverted at a later time. table 49. cfi system interface string byte address data description 1bh 27h v cc min. (erase/program): 100 millivolts 1ch 36h v cc max. (erase/program): 100 millivolts 1dh 00h v pp min. voltage (00h = no v pp present) 1eh 00h v pp max. voltage (00h = no v pp present) 1fh 06h typical timeout per single byte program 2 n s 20h 0ah (256b page) 0ah (512b page) typical timeout for min. size page program 2 n s (00h = not supported) 21h 08h (4 kb or 64 kb) 0ah (256 kb) typical timeout per individual sector erase 2 n ms 22h 0fh (128 mb) typical timeout for full chip erase 2 n ms (00h = not supported) 23h 02h max. timeout for byte program 2 n times typical 24h 02h max. timeout for page program 2 n times typical 25h 03h max. timeout per individual sector erase 2 n times typical 26h 03h max. timeout for full chip erase 2 n times typical (00h = not supported) table 50. device geometry definition for bottom boot initial delivery state byte address data description 27h 18h (128 mb) device size = 2 n bytes; 28h 02h flash device interface description; 0000h = x8 only 0001h = x16 only 0002h = x8/x16 capable 0003h = x32 only 0004h = single i/o spi, 3-byte address 0005h = multi i/o spi, 3-byte address 0102h = multi i/o spi, 3- or 4-byte address 29h 01h 2ah 08h max. number of bytes in multi-byte write = 2 n (0000 = not supported 0008h = 256b page 0009h = 512b page) 2bh 00h 2ch 02h number of erase block regions within device 1 = uniform device, 2 = boot device 2dh 0fh erase block region 1 information (refer to jedec jep137) 16 sectors = 16-1 = 000fh 4-kb sectors = 256 bytes x 0010h 2eh 00h 2fh 10h 30h 00h 31h feh erase block region 2 information 255 sectors = 255-1 = 00feh (128 mb) 64-kb sectors = 0100h x 256 bytes 32h 00h (128 mb) 33h 00h 34h 01h 35h thru 3fh ffh rfu document number: 001-98282 rev. *i page 120 of 142 S25FL127S table 51. device geometry defi nition for uniform sector devices byte address data description 27h 18h (128 mb) device size = 2 n bytes; 28h 02h flash device interface description; 0000h = x8 only 0001h = x16 only 0002h = x8/x16 capable 0003h = x32 only 0004h = single i/o spi, 3-byte address 0005h = multi i/o spi, 3-byte address 0102h = multi i/o spi, 3- or 4-byte address 29h 01h 2ah 09h max. number of bytes in multi-byte write = 2 n (0000 = not supported 0008h = 256b page 0009h = 512b page) 2bh 00h 2ch 01h number of erase block regions within device 1 = uniform device, 2 = boot device 2dh 3fh (128 mb) erase block region 1 information (refer to jedec jep137) 64 sectors = 64-1 = 003fh (128 mb) 256-kb sectors = 256 bytes x 0400h 2eh 00h 2fh 00h 30h 04h 31h thru 3fh ffh rfu table 52. cfi primary vendor-specific extended query byte address data description 40h 50h query-unique ascii string ?pri? 41h 52h 42h 49h 43h 31h major version number = 1, ascii 44h 33h minor version number = 3, ascii 45h 21h address sensitive unlock (bits 1-0) 00b = required 01b = not required process technology (bits 5-2) 0000b = 0.23 m floating gate 0001b = 0.17 m floating gate 0010b = 0.23 m mirrorbit 0011b = 0.11 m floating gate 0100b = 0.11 m mirrorbit 0101b = 0.09 m mirrorbit 1000b = 0.065 m mirrorbit 46h 02h erase suspend 0 = not supported 1 = read only 2 = read and program 47h 01h sector protect 00 = not supported x = number of sectors in group document number: 001-98282 rev. *i page 121 of 142 S25FL127S the alternate vendor-specific extended query provides informati on related to the expanded command set provided by the fl-s family. the alternate query parameters use a format in which ea ch parameter begins with an ident ifier byte and a parameter leng th byte. driver software can check each parameter id and can use t he length value to skip to the next parameter if the parameter i s not needed or not recognized by the software. 48h 00h temporary sector unprotect 00 = not supported 01 = supported 49h 08h sector protect/unprotect scheme 04 = high voltage method 05 = software command locking method 08 = advanced sector protection method 09 = secure 4ah 00h simultaneous operation 00 = not supported x = number of sectors 4bh 01h burst mode (synchronous sequential read) support 00 = not supported 01 = supported 4ch model dependent 03h (models x0) 04h (models x1) page mode type, model dependent 00 = not supported 01 = 4 word read page 02 = 8 read word page 03 = 256-byte program page 04 = 512-byte program page 4dh 00h acc (acceleration) supply minimum 00 = not supported, 100 mv 4eh 00h acc (acceleration) supply maximum 00 = not supported, 100 mv 4fh 07h wp# protection 01 = whole chip 04 = uniform device with bottom wp protect 05 = uniform device with top wp protect 07 = uniform device with top or bo ttom write protect (user select) 50h 01h program suspend 00 = not supported 01 = supported table 53. cfi alternate vendor-specific extended query header byte address data description 51h 41h query-unique ascii string ?alt? 52h 4ch 53h 54h 54h 32h major version number = 2, ascii 55h 30h minor version number = 0, ascii table 52. cfi primary vendor-specific extended query (continued) byte address data description document number: 001-98282 rev. *i page 122 of 142 S25FL127S table 54. cfi alternate vendor-specific extended query parameter 0 parameter relative byte address offset data description 00h 00h parameter id (ordering part number) 01h 10h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 53h ascii ?s? for manufacturer (cypress) 03h 32h ascii ?25? for product characters (single die spi) 04h 35h 05h 46h ascii ?fl? for interface characters (spi 3 volt) 06h 4ch 07h 31h (128 mb) ascii characters for density 08h 32h (128 mb) 09h 38h (128 mb) 0ah 53h ascii ?s? for technology (65 nm mirrorbit) 0bh 41h ascii characters for speed grade refer to ordering information on page 141 for the speed grade definitions. 0ch 42h 0dh 3fh ascii ???? for package (generally t he package is not specified for an individual memory device because the choice of package is generally made after the device is tested and this parameter is programmed. however, space is provided in this parameter for special cases where devices are tested and programmed for use only in a specific package) 0eh 3fh 0fh 49h ascii character for temperature range 10h xxh ascii characters for model refer to ordering information on page 141 for the model number definitions. 11h xxh table 55. cfi alternate vendor-specific extended query parameter 80h address options parameter relative byte address offset data description 00h 80h parameter id (address options) 01h 01h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h f0h bits 7:4 - reserved = 1111b bit 3 - autoboot support - ye s= 0b, no = 1b bit 2 - 4-byte address instructions supported - yes = 0b, no = 1b bit 1 - bank address + 3-byte address instructions supported - yes = 0b, no = 1b bit 0 - 3-byte address instructions supported - yes = 0b, no = 1b document number: 001-98282 rev. *i page 123 of 142 S25FL127S table 56. cfi alternate vendor-specific extended query parameter 84h suspend commands parameter relative byte address offset data description 00h 84h parameter id (suspend commands 01h 08h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 85h program suspend instruction code 03h 2dh program suspend latency maximum (s) 04h 8ah program resume instruction code 05h 64h program resume to next suspend typical (s) 06h 75h erase suspend instruction code 07h 2dh erase suspend latency maximum (s) 08h 7ah erase resume instruction code 09h 64h erase resume to ne xt suspend typical (s) table 57. cfi alternate vendor-specific extended query parameter 88h data protection parameter relative byte address offset data description 00h 88h parameter id (data protection) 01h 04h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 0ah otp size 2 n bytes, ffh = not supported 03h 01h otp address map format, 01h = fl-s format, ffh = not supported 04h xxh block protect type, model dependent 00h = fl-p, fl-s, ffh = not supported 05h xxh advanced sector protection type, model dependent 01h = fl-s asp. table 58. cfi alternate vendor-specific extended query parameter 8ch reset timing parameter relative byte address offset data description 00h 8ch parameter id (reset timing) 01h 06h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 96h por maximum value 03h 01h por maximum exponent 2 n s 04h ffh (without reset# input) 23h (with reset# input) hardware reset maximum value 05h 00h hardware reset maximum exponent 2 n s 06h 23h software reset maximum value, ffh = not supported 07h 00h software reset maximum exponent 2 n s document number: 001-98282 rev. *i page 124 of 142 S25FL127S table 59. cfi alternate vendor-specific extended query parameter 90h ? latency code parameter relative byte address offset data description 00h 90h parameter id (latency code table) 01h 56h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 06h number of rows 03h 0eh row length in bytes 04h 46h start of header (row 1), ascii ?f? for frequency column header 05h 43h ascii ?c? for code column header 06h 03h read 3-byte address instruction 07h 13h read 4-byte address instruction 08h 0bh read fast 3-byte address instruction 09h 0ch read fast 4-byte address instruction 0ah 3bh read dual out 3-byte address instruction 0bh 3ch read dual out 4-byte address instruction 0ch 6bh read quad out 3-byte address instruction 0dh 6ch read quad out 4-byte address instruction 0eh bbh dual i/o read 3-byte address instruction 0fh bch dual i/o read 4-byte address instruction 10h ebh quad i/o read 3-byte address instruction 11h ech quad i/o read 4-byte address instruction 12h 32h start of row 2, sck frequency limit for this row (50 mhz) 13h 03h latency code for this row (11b) 14h 00h read mode cycles 15h 00h read latency cycles 16h 00h read fast mode cycles 17h 00h read fast latency cycles 18h 00h read dual out mode cycles 19h 00h read dual out latency cycles 1ah 00h read quad out mode cycles 1bh 00h read quad out latency cycles 1ch 04h dual i/o read mode cycles 1dh 00h dual i/o read latency cycles 1eh 02h quad i/o read mode cycles 1fh 01h quad i/o read latency cycles 20h 50h start of row 3, sck frequency limit for this row (80 mhz) 21h 00h latency code for this row (00b) 22h ffh read mode cycles (ffh = command not supported at this frequency) 23h ffh read latency cycles 24h 00h read fast mode cycles document number: 001-98282 rev. *i page 125 of 142 S25FL127S 25h 08h read fast latency cycles 26h 00h read dual out mode cycles 27h 08h read dual out latency cycles 28h 00h read quad out mode cycles 29h 08h read quad out latency cycles 2ah 04h dual i/o read mode cycles 2bh 00h dual i/o read latency cycles 2ch 02h quad i/o read mode cycles 2dh 04h quad i/o read latency cycles 2eh 5ah start of row 4, sck frequency limit for this row (90 mhz) 2fh 01h latency code for this row (01b) 30h ffh read mode cycles (ffh = command not supported at this frequency) 31h ffh read latency cycles 32h 00h read fast mode cycles 33h 08h read fast latency cycles 34h 00h read dual out mode cycles 35h 08h read dual out latency cycles 36h 00h read quad out mode cycles 37h 08h read quad out latency cycles 38h 04h dual i/o read mode cycles 39h 01h dual i/o read latency cycles 3ah 02h quad i/o read mode cycles 3bh 04h quad i/o read latency cycles 3ch 68h start of row 5, sck frequency limit for this row (108 mhz) 3dh 02h latency code for this row (10b) 3eh ffh read mode cycles (ffh = command not supported at this frequency) 3fh ffh read latency cycles 40h 00h read fast mode cycles 41h 08h read fast latency cycles 42h 00h read dual out mode cycles 43h 08h read dual out latency cycles 44h 00h read quad out mode cycles 45h 08h read quad out latency cycles 46h 04h dual i/o read mode cycles 47h 02h dual i/o read latency cycles 48h 02h quad i/o read mode cycles 49h 05h quad i/o read latency cycles 4ah 85h start of row 6, sck frequency limit for this row (133 mhz) table 59. cfi alternate vendor-specific extended query parameter 90h ? latency code (continued) parameter relative byte address offset data description document number: 001-98282 rev. *i page 126 of 142 S25FL127S this parameter type (param eter id f0h) may appear multiple times and have a di fferent length each time. the parameter is used t o reserve space in the id-cfi map or to force space (pad) to align a following parameter to a required boundary. 4bh 02h latency code for this row (10b) 4ch ffh read mode cycles (ffh = command not supported at this frequency) 4dh ffh read latency cycles 4eh 00h read fast mode cycles 4fh 08h read fast latency cycles 50h ffh read dual out mode cycles 51h ffh read dual out latency cycles 52h ffh read quad out mode cycles 53h ffh read quad out latency cycles 54h ffh dual i/o read mode cycles 55h ffh dual i/o read latency cycles 56h ffh quad i/o read mode cycles 57h ffh quad i/o read latency cycles table 60. cfi alternate vendor-specific extended query parameter f0h rfu parameter relative byte address offset data description 00h f0h parameter id (rfu) 01h 0fh parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h ffh rfu ... ffh rfu 10h ffh rfu table 61. cfi alternate vendor-specific extended query parameter a5h, jedec sfdp rev b cfi parameter relative byte address offset sfdp parameter relative byte address offset sfdp dword name data description 00h ? n/a a5h cfi parameter id (a5h = jedec sfdp) 01h ? n/a 80h cfi parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 00h jedec basic flash parameter dword-1 e7h start of sfdp jedec parameter, located at 1120h in the overall sfdp address space. bits 7:5 = unused = 111b bit 4:3 = 06h is status register write instruct ion & status register is default non-volatile= 00b bit 2 = program buffer > 64bytes = 1 bits 1:0 = uniform 4kb erase unavailable = 11b 03h 01h ffh bits 15:8 = uniform 4kb erase opcode = not supported = ffh 04h 02h f3h (flxxxsa g) bit 23 = unused = 1b bit 22 = supports quad out read, yes = 1b bit 21 = supports quad i/o read, yes =1b bit 20 = supports dual i/o read, yes = 1b bit19 = supports ddr, no = 0h bit 18:17 = number of address bytes, 3 or 4 = 01b bit 16 = supports dual out read, yes = 1b 05h 03h ffh bits 31:24 = unused = ffh table 59. cfi alternate vendor-specific extended query parameter 90h ? latency code (continued) parameter relative byte address offset data description document number: 001-98282 rev. *i page 127 of 142 S25FL127S 06h 04h jedec basic flash parameter dword-2 ffh density in bits, zero based, 128mb = 07ffffffh 07h 05h ffh 08h 06h ffh 09h 07h 07h 0ah 08h jedec basic flash parameter dword-3 44h bits 7:5 = number of quad i/o mode cycles = 010b bits 4:0 = number of quad i/o dummy cycl es = 00100b for default latency code 00b 0bh 09h ebh quad i/o instruction code 0ch 0ah 08h bits 23:21 = number of quad out mode cycles = 000b bits 20:16 = number of quad out dummy cycles = 01000b 0dh 0bh 6bh quad out instruction code 0eh 0ch jedec basic flash parameter dword-4 08h bits 7:5 = number of dual out mode cycles = 000b bits 4:0 = number of dual out dummy cycles = 01000b for default latency code 0fh 0dh 3bh dual out instruction code 10h 0eh 80h bits 23:21 = number of dual i/o mode cycles 20:16 = number of dual i/o dummy cycles default latency code = 00b 11h 0fh bbh dual i/o instruction code 12h 10h jedec basic flash parameter dword-5 eeh bits 7:5 rfu = 111b bit 4 = quad all not supported = 0b bits 3:1 rfu = 111b bit 0 = dual all not supported = 0b 13h 11h ffh bits 15:8 = rfu = ffh 14h 12h ffh bits 23:16 = rfu = ffh 15h 13h ffh bits 31:24 = rfu = ffh 16h 14h jedec basic flash parameter dword-6 ffh bits 7:0 = rfu = ffh 17h 15h ffh bits 15:8 = rfu = ffh 18h 16h ffh bits 23:21 = number of dual all mode cycles = 111b bits 20:16 = number of dual all dummy cycles = 11111b 19h 17h ffh dual all instruction code 1ah 18h jedec basic flash parameter dword-7 ffh bits 7:0 = rfu = ffh 1bh 19h ffh bits 15:8 = rfu = ffh 1ch 1ah ffh bits 23:21 = number of quad all mode cycles = 111b bits 20:16 = number of quad all dummy cycles = 11111b 1dh 1bh ffh quad all instruction code 1eh 1ch jedec basic flash parameter dword-8 0ch erase type 1 size 2 n bytes = 4kb = 0ch (for hybrid sector initial delivery state) 1fh 1dh 20h erase type 1 instruction 20h 1eh 10h erase type 2 size 2 n bytes = 64kb = 10h (for hybrid sector initial delivery state) 21h 1fh d8h erase type 2 instruction 22h 20h jedec basic flash parameter dword-9 12h erase type 3 size 2 n bytes = 256kb = 12h (if uniform sectors enabled) 23h 21h d8h erase type 3 instruction 24h 22h 00h erase type 4 size 2 n bytes = not supported = 00h 25h 23h ffh erase type 4 instruction = not supported = ffh table 61. cfi alternate vendor-specific extended query parameter a5h, jedec sfdp rev b (continued) cfi parameter relative byte address offset sfdp parameter relative byte address offset sfdp dword name data description document number: 001-98282 rev. *i page 128 of 142 S25FL127S 26h 24h jedec basic flash parameter dword-10 82h bits 31:30 = erase type 4 erase, typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s) = rfu = 11b bits 29:25 = erase type 4 erase, typical time count = rfu = 11111b ( typ erase time = count +1 * units = rfu ) bits 24:23 = erase type 3 erase, typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s) = 128ms = 10b bits 22:18 = erase type 3 erase, typical ti me count = 00011b ( typ erase time = count +1 * units = 4*128ms = 512ms) bits 17:16 = erase type 2 erase, typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s) = 128ms = 10b bits 15:11 = erase type 2 erase, typical time count = 00000b ( typ erase time = count +1 * units = 1*128ms = 128ms) bits 10:9 = erase type 1 erase, typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s) = 16ms = 01b bits 8:4 = erase type 1 erase, typical time count = 01000b ( typ erase time = count +1 * units = 9*16ms = 144ms) bits 3:0 = multiplier from typical erase time to maximum erase time = 2*(n+1), n=2h = 6x multiplier binary fields: 11-11111-10-00011-10-00000-01-01000-0 010 nibble format: 1111_1111_0000_1110_0000_0010_1000_0010 hex format: ff_0e_02_82 27h 25h 02h 28h 26h 0eh 29h 27h ffh 2ah 28h jedec basic flash parameter dword-11 92h bit 31 reserved = 1b bits 30:29 = chip erase, typical time units (00b: 16 ms, 01b: 256 ms, 10b: 4 s, 11b: 64 s) = 4s = 10b bits 28:24 = chip erase, typical time count, (count+1)*units, count = 01000b, ( typ program time = count +1 * units = 9*4s = 36s bits 23 = byte program typical time, additional byte units (0b:1us, 1b:8us) = 1us = 0b bits 22:19 = byte program typical time, additi onal byte count, (count+1)*units, count = 0000b, ( typ program time = count +1 * units = 1*1us = 1us bits 18 = byte program typical time, first byte units (0b:1us, 1b:8us) = 8us = 1b bits 17:14 = byte program typical time, first byte count, (count+1)*units, count = 1100b, ( typ program time = count +1 * units = 13*8us = 104us bits 13 = page program typical time units (0b:8us, 1b:64us) = 64us = 1b bits 12:8 = page program typical time count, (count+1)*units, count = 01001b, ( typ program time = count +1 * units = 10*64us = 640us) bits 7:4 = page size 2^n, n=9h, = 512b page bits 3:0 = multiplier from typical time to maximum for page or byte program = 2*(n+1), n=2h = 6x multiplier binary fields: 1-10-01000-0-0000-1-1100-1-01001-1001-0010 nibble format: 1100_1000_0000_0111_0010_1001_1001_0010 hex format: c8_07_29_92 2bh 29h 29h 2ch 2ah 07h 2dh 2bh c8h 2eh 2ch jedec basic flash parameter dword-12 ech bit 31 = suspend and resume supported = 0b bits 30:29 = suspend in-progress erase max latency units (00b: 128ns, 01b: 1us, 10b: 8us, 11b: 64us) = 8us= 10b bits 28:24 = suspend in-progress erase max latency count = 00101b, max erase suspend latency = count +1 * units = 6*8us = 48us bits 23:20 = erase resume to suspend inte rval count = 0001b, interval = count +1 * 64us = 2 * 64us = 128us bits 19:18 = suspend in-progress program max latency units (00b: 128ns, 01b: 1us, 10b: 8us, 11b: 64us) = 8us= 10b bits 17:13 = suspend in-progress program max latency count = 00101b, max erase suspend latency = count +1 * units = 6*8us = 48us bits 12:9 = program resume to suspend interval count = 0001b, interval = count +1 * 64us = 2 * 64us = 128us bit 8 = rfu = 1b bits 7:4 = prohibited operations during erase suspend = xxx0b: may not initiate a new erase anywhere (erase nesting not permitted) + xx1xb: may not initiate a page program in the erase suspended sector size + x1xxb: may not initiate a read in the eras e suspended sector size + 1xxxb: the erase and program restrictions in bits 5:4 are sufficient = 1110b bits 3:0 = prohibited operations during program suspend = xxx0b: may not initiate a new erase anywhere (erase nesting not permitted) + xx0xb: may not initiate a new page program anywhere (program nesting not permitted) + x1xxb: may not initiate a read in the program suspended page size + 1xxxb: the erase and program restrictions in bits 1:0 are sufficient = 1100b binary fields: 0-10-00101-0001-10-00101-0001-1-1110-1100 nibble format: 0100_0101_0001_1000_1010_0011_1110_1100 hex format: 45_18_a3_ec 2fh 2dh a3h 30h 2eh 18h 31h 2fh 45h 32h 30h jedec basic flash parameter dword-13 8ah bits 31:24 = erase suspend instruction = 75h bits 23:16 = erase resume instruction = 7ah bits 15:8 = program suspend instruction = 85h bits 7:0 = program resume instruction = 8ah 33h 31h 85h 34h 32h 7ah 35h 33h 75h table 61. cfi alternate vendor-specific extended query parameter a5h, jedec sfdp rev b (continued) cfi parameter relative byte address offset sfdp parameter relative byte address offset sfdp dword name data description document number: 001-98282 rev. *i page 129 of 142 S25FL127S 36h 34h jedec basic flash parameter dword-14 f7h bit 31 = deep power down supported = not supported = 1 bits 30:23 = enter deep power down instruction = not supported = ffh bits 22:15 = exit deep power down instruction = not supported = ffh bits 14:13 = exit deep power down to next operation delay units = (00b: 128ns, 01b: 1us, 10b: 8us, 11b: 64us) = 64us = 11b bits 12:8 = exit deep power down to next operation delay count = 11111b, exit deep power down to next operation delay = (count+1)*units = not supported bits 7:4 = rfu = fh bit 3:2 = status register polling device busy = 01b: legacy status polling supported = use legacy polling by reading the status register with 05h instruction and checking wip bit[0] (0=ready; 1=busy). bits 1:0 = rfu = 11b binary fields: 1-11111111-11111111-11-11111-1111-01-11 nibble format: 1111_1111_1111_1111_1111_1111_1111_0111 hex format: ff_ff_ff_f7 37h 35h ffh 38h 36h ffh 39h 37h ffh 3ah 38h jedec basic flash parameter dword-15 00h bits 31:24 = rfu = ffh bit 23 = hold and wp disable = not supported = 0b bits 22:20 = quad enable requirements = 101b: qe is bit 1 of the status register 2 (sfdp spec calls this status register 2, fl127s calls this configuration register 1). status register 1 is read using read status instruction 05h. status register 2 (fl127s configuration register 1) is read using instruction 35h. qe is set via write status instruction 01h with two data bytes where bit 1 of the second byte is one. it is cleared via write status with two data bytes where bit 1 of the second byte is zero. bits 19:16 0-4-4 mode entry method = xxx1b: mode bits[7:0] = a5h note: qe must be set prior to using this mode + x1xxb: mode bits[7:0] = axh + 1xxxb: rfu = 1101b bits 15:10 0-4-4 mode exit method = xx_xxx1b: mode bits[7:0] = 00h will terminate this mode at the end of the current read operation + xx_1xxxb: input fh (mode bit reset) on dq0-dq3 for 8 clocks. this will terminate the mode prior to the next read operation. + x1_xxxxb: mode bit[7:0] != axh + 1x_x1xx: rfu = 11_1101 bit 9 = 0-4-4 mode supported = 1 bits 8:4 = 4-4-4 mode enable sequences = 0_0000b: 4-4-4 not supported = 00000b bits 3:0 = 4-4-4 mode disable sequences = 0000b: 4-4-4 not supported = 0000b binary fields: 11111111-0-101-1101-111101-1-00000-0000 nibble format: 1111_1111_0101_1101_ 1111_0110_0000_0000 hex format: ff_5d_f6_00 3bh 39h f6h 3ch 3ah 5dh 3dh 3bh ffh table 61. cfi alternate vendor-specific extended query parameter a5h, jedec sfdp rev b (continued) cfi parameter relative byte address offset sfdp parameter relative byte address offset sfdp dword name data description document number: 001-98282 rev. *i page 130 of 142 S25FL127S 3eh 3ch jedec basic flash parameter dword-16 f0h bits 31:24 = enter 4-byte addressing = xxxx_1xxxb: 8-bit volatile bank register used to define a[30:a24] bits. msb (bit[7]) is used to enable/disable 4-byte address mode. when msb is set to ?1?, 4-byte address mode is active and a[30:24] bits are don?t care. read with instruction 16h. write instruction is 17h with 1 byte of data. when msb is cleared to ?0?, select the active 128 mbit segment by setting the appropriate a[30:24] bits and use 3-byte addressing. + xx1x_xxxxb: supports dedicated 4-byte address instruction set. consult vendor data sheet for the instruction set definition or look for 4 byte address parameter table. + 1xxx_xxxxb: reserved = 10101000b bits 23:14 = exit 4-byte addressing = xx_xxxx_1xxxb: 8-bit volatile bank register used to define a[30:a24] bits. msb (bit[7]) is used to enable/disable 4-byte address mode. when msb is cleared to ?0?, 3-byte address mode is active and a30:a24 ar e used to select the active 128 mbit memory segment. read with instruction 16h. write instruction is 17h, data length is 1 byte. + xx_xx1x_xxxxb: hardware reset + xx_x1xx_xxxxb: software reset (see bits 13:8 in this dword) + xx_1xxx_xxxxb: power cycle + x1_xxxx_xxxxb: reserved + 1x_xxxx_xxxxb: reserved = 1 11110 1000b bits 13:8 = soft reset and rescue sequence support = x0_1xxxb: issue instruction f0h + 1x_xxxxb: exit 0-4-4 mode is required prio r to other reset sequences above if the device may be operating in this mode. = 101000b bit 7 = rfu = 1 bits 6:0 = volatile or non-volatile register and write enable instruction for status register 1 = xx1_xxxxb: status register 1 contains a mi x of volatile and non-v olatile bits. the 06h instruction is used to enable writing of the register. + x1x_xxxxb: reserved + 1xx_xxxxb: reserved = 1110000b binary fields: 10101000- 1111101 000-101000-1-1110000 nibble format: 1010_1000_ 1111_1010_0010_1000_ 1111_0000 hex format: a8_fa_28_f0 3fh 3dh 28h 40h 3eh fah 41h 3fh a8h 42h 40h jedec sector map parameter dword-1 config. detect-1 fch bits 31:24 = read data mask = 10000000b: select bit 7 of the data byte for d8h_o value bits 23:22 = configuration detection command address length = 00b: no address bits 21:20 = rfu = 11b bits 19:16 = configuration detection command latency = 0000b: zero latency bits 15:8 = configuration detection instruction = 07h: read status register 2 bits 7:2 = rfu = 111111b bit 1 = command descriptor = 0 bit 0 = not the end descriptor = 0 binary fields: 10000000-00-11-0000-00000111-111111-0-0 nibble format: 1000_0000_0011_0000_0000_0111_ 1111_1100 hex format: 80_30_07_fc 43h 41h 07h 44h 42h 30h 45h 43h 80h 46h 44h jedec sector map parameter dword-2 config. detect-1 ffh bits 31:0 = sector map configuration detection command address = ffffh: no address 47h 45h ffh 48h 46h ffh 49h 47h ffh 4ah 48h jedec sector map parameter dword-3 config. detect-2 fdh bits 31:24 = read data mask = 00000100b: select bit 2 of the data byte for tbparm value bits 23:22 = configuration detection command address length = 00b: no address bits 21:20 = rfu = 11b bits 19:16 = configuration detection command latency = 0000b: zero latency bits 15:8 = configuration detection instruction = 35h: read configuration register 1 bits 7:2 = rfu = 111111b bit 1 = command descriptor = 0 bit 0 = the end descriptor = 1 binary fields: 00000100-00-11-0000-00110101- 111111-0-1 nibble format: 0000_0100_0011_0000_0011_0101_ 1111_1101 hex format: 04_30_35_fd 4bh 49h 35h 4ch 4ah 30h 4dh 4bh 04h 4eh 4ch jedec sector map parameter dword-4 config. detect-2 ffh bits 31:0 = sector map configuration detection command address = ffffh: no address 4fh 4dh ffh 50h 4eh ffh 51h 4fh ffh table 61. cfi alternate vendor-specific extended query parameter a5h, jedec sfdp rev b (continued) cfi parameter relative byte address offset sfdp parameter relative byte address offset sfdp dword name data description document number: 001-98282 rev. *i page 131 of 142 S25FL127S 52h 50h jedec sector map parameter dword-5 config-0 header feh bits 31:24 = rfu = ffh bits 23:16 = region count (dwords -1) = 01h: two regions bits 15:8 = configuration id = 00h: 4kb sectors at bottom with remainder 64kb sectors bits 7:2 = rfu = 111111b bit 1 = map descriptor = 1 bit 0 = not the end descriptor = 0 53h 51h 00h 54h 52h 01h 55h 53h ffh 56h 54h jedec sector map parameter dword-6 config-0 region-0 f3h bits 31:8 = region size = 0000ffh: region size as count-1 of 256 byte units = 16 x 4kb sectors = 64kb count = 64kb/256 = 256, value = count -1 = 256 -1 = 255 = ffh bits 7:4 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 0b ---erase type 3 is 256kb erase and is not supported in the 4kb sector region bit 1 = erase type 2 support = 1b ---erase type 2 is 64kb erase and is supported in the 4kb sector region bits 0 = erase type 1 support = 1b ---erase type 1 is 4kb erase and is supported in the 4kb sector region 57h 55h ffh 58h 56h 00h 59h 57h 00h 5ah 58h jedec sector map parameter dword-7 config-0 region-1 f2h bits 31:8 = region size = 00feffh: region size as count-1 of 256 byte units = 255 x 64kb sectors = 16320kb count = 16320kb/256 = 65280, value = count -1 = 65280 -1 = 65279 = feffh bits 4:7 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 0b ---erase type 3 is 256kb erase and is not supported in the 64kb sector region bit 1 = erase type 2 support = 1b ---erase type 2 is 64kb erase and is supported in the 64kb sector region bit 0 = erase type 1 support = 0b --- erase type 1 is 4kb erase and is not supported in the 64kb sector region 5bh 59h ffh 5ch 5ah feh 5dh 5bh 00h 5eh 5ch jedec sector map parameter dword-8 config-1 header feh bits 31:24 = rfu = ffh bits 23:16 = region count (dwords -1) = 01h: two regions bits 15:8 = configuration id = 01h: 4kb sectors at top with remainder 64kb sectors bits 7:2 = rfu = 111111b bit 1 = map descriptor = 1 bit 0 = not the end descriptor = 0 5fh 5dh 01h 60h 5eh 01h 61h 5fh ffh 62h 60h jedec sector map parameter dword-9 config-1 region-0 f2h bits 31:8 = region size = 00feffh: region size as count-1 of 256 byte units = 255 x 64kb sectors = 16320kb count = 16320kb/256 = 65280, value = count -1 = 65280 -1 = 65279 = feffh bits 4:7 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 0b ---erase type 3 is 256kb erase and is not supported in the 64kb sector region bit 1 = erase type 2 support = 1b ---erase type 2 is 64kb erase and is supported in the 64kb sector region bit 0 = erase type 1 support = 0b --- erase type 1 is 4kb erase and is not supported in the 64kb sector region 63h 61h ffh 64h 62h feh 65h 63h 00h 66h 64h jedec sector map parameter dword-10 config-1 region-1 f3h bits 31:8 = region size = 0000ffh: region size as count-1 of 256 byte units = 16 x 4kb sectors = 64kb count = 64kb/256 = 256, value = count -1 = 256 -1 = 255 = ffh bits 7:4 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 0b ---erase type 3 is 256kb erase and is not supported in the 4kb sector region bit 1 = erase type 2 support = 1b ---erase type 2 is 64kb erase and is supported in the 4kb sector region bit 0 = erase type 1 support = 1b ---erase type 1 is 4kb erase and is supported in the 4kb sector region 67h 65h ffh 68h 66h 00h 69h 67h 00h 6ah 68h jedec sector map parameter dword-11 config-2 header feh bits 31:24 = rfu = ffh bits 23:16 = region count (dwords -1) = 00h: one region bits 15:8 = configuration id = 02h: uniform 256kb sectors bits 7:2 = rfu = 111111b bit 1 = map descriptor = 1 bit 0 = the end descriptor = 0 6bh 69h 02h 6ch 6ah 00h 6dh 6bh ffh table 61. cfi alternate vendor-specific extended query parameter a5h, jedec sfdp rev b (continued) cfi parameter relative byte address offset sfdp parameter relative byte address offset sfdp dword name data description document number: 001-98282 rev. *i page 132 of 142 S25FL127S 6eh 6ch jedec sector map parameter dword-12 config-2 region-0 f4h bits 31:8 = region size = 00ffffh: region size as count-1 of 256 byte units = 16mb/256 = 64k count = 65536, value = count -1 = 65536 -1 = 65535 = ffffh bits 4:7 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 1b ---erase type 3 is 256kb erase and is supported in the 256kb sector region bit 1 = erase type 2 support = 0b ---erase type 2 is 64kb erase and is not supported in the 256kb sector region bit 0 = erase type 1 support = 0b --- erase type 1 is 4kb erase and is not supported in the 256kb sector region 6fh 6dh ffh 70h 6eh ffh 71h 6fh 00h 72h 70h jedec sector map parameter dword-13 config-3 header ffh bits 31:24 = rfu = ffh bits 23:16 = region count (dwords -1) = 00h: one region bits 15:8 = configuration id = 03h: uniform 256kb sectors bits 7:2 = rfu = 111111b bit 1 = map descriptor = 1 bit 0 = the end descriptor = 1 73h 71h 03h 74h 72h 00h 75h 73h ffh 76h 74h jedec sector map parameter dword-14 config-3 region-0 f4h bits 31:8 = region size = 00ffffh: region size as count-1 of 256 byte units = 16mb/256 = 64k count = 65536, value = count -1 = 65536 -1 = 65535 = ffffh bits 4:7 = rfu = fh erase type not supported = 0/ supported = 1 bit 3 = erase type 4 support = 0b ---erase type 4 is not defined bit 2 = erase type 3 support = 1b ---erase type 3 is 256kb erase and is supported in the 256kb sector region bit 1 = erase type 2 support = 0b ---erase type 2 is 64kb erase and is not supported in the 256kb sector region bit 0 = erase type 1 support = 0b --- erase type 1 is 4kb erase and is not supported in the 256kb sector region 77h 75h ffh 78h 76h ffh 79h 77h 00h 7ah 78h jedec 4 byte address instructions parameter dword-1 ffh supported = 1, not supported = 0 bits 31:20 = rfu = fffh bit 19 = support for non-volatile individual sector lock write command, instruction=e3h = 1 bit 18 = support for non-volatile individual sector lock read command, instruction=e2h = 1 bit 17 = support for volatile individual sect or lock write command, instruction=e1h = 1 bit 16 = support for volatile individual sector lock read command, instruction=e0h = 1 bit 15 = support for (1-4-4) dtr_read command, instruction=eeh = 0 bit 14 = support for (1-2-2) dtr_read command, instruction=beh = 0 bit 13 = support for (1-1-1) dtr_read command, instruction=0eh = 0 bit 12 = support for erase command ? type 4 = 0 bit 11 = support for erase command ? type 3 = 1 bit 10 = support for erase command ? type 2 = 1 bit 9 = support for erase command ? type 1 = 1 bit 8 = support for (1-4-4) page program command, instruction=3eh =0 bit 7 = support for (1-1-4) page program command, instruction=34h = 1 bit 6 = support for (1-1-1) page program command, instruction=12h = 1 bit 5 = support for (1-4-4) fast_read command, instruction=ech = 1 bit 4 = support for (1-1-4) fast_read command, instruction=6ch = 1 bit 3 = support for (1-2-2) fast_read command, instruction=bch = 1 bit 2 = support for (1-1-2) fast_read command, instruction=3ch = 1 bit 1 = support for (1-1-1) fast_read command, instruction=0ch = 1 bit 0 = support for (1-1-1) read command, instruction=13h = 1 7bh 79h 0eh 7ch 7ah ffh 7dh 7bh ffh 7eh 7ch jedec 4 byte address instructions parameter dword-2 21h bits 31:24 = ffh = instruction for erase type 4: rfu bits 23:16 = dch = instruction for erase type 3 bits 15:8 = dch = instruction for erase type 2 bits 7:0 = 21h = instruction for erase type 1 7fh 7dh dch 80h 7eh dch 81h 7fh ffh table 61. cfi alternate vendor-specific extended query parameter a5h, jedec sfdp rev b (continued) cfi parameter relative byte address offset sfdp parameter relative byte address offset sfdp dword name data description document number: 001-98282 rev. *i page 133 of 142 S25FL127S 12.3 device id and common flash interf ace (id-cfi) aso ma p ? automotive only the cfi primary vendor-sp ecific extended query is extended to include electronic marking information for device traceability fab lot # + wafer # + die x coordinate + die y coordinate gives a unique id for each device. address data field # of bytes data format example of actual data hex read out of example data (sa) + 0180h size of electronic marking 1 hex 20 14h (sa) + 0181h revision of electronic marking 1 hex 1 01h (sa) + 0182h fab lot # 8 ascii ld87270 4ch, 44h, 38h, 37h, 32h, 37h, 30h, ffh (sa) + 018ah wafer # 1 hex 23 17h (sa) + 018bh die x coordinate 1 hex 10 0ah (sa) + 018ch die y coordinate 1 hex 15 0fh (sa) + 018dh class lot # 7 ascii br3315 0 42h, 52h, 33h, 33h, 31h, 35h, 30h (sa) + 0194h reserved for future 12 n/a n/a ffh, ffh, ffh, ffh, ffh, ffh, ffh, ffh, ffh, ffh, ffh, ffh document number: 001-98282 rev. *i page 134 of 142 S25FL127S 12.4 registers the register maps are copied in this section as a quick reference. see registers on page 50 for the full description of the register contents. table 62. status register 1 (sr1) bits field name function type default state description 7 srwd status register write disable non-volatile 0 1 = locks state of srwd, bp, and configuration register bits when wp# is low by ignoring wrr command 0 = no protection, even when wp# is low 6 p_err programming error occurred volatile, read only 0 1 = error occurred 0 = no error 5 e_err erase error occurred volatile, read only 0 1= error occurred 0 = no error 4 bp2 block protection volatile if cr1[3]=1, non-volatile if cr1[3]=0 1 if cr1[3]=1, 0 when shipped from cypress protects selected range of sectors (block) from program or erase 3 bp1 2 bp0 1 wel write enable latch volatile 0 1 = device accepts write registers (wrr), program or erase commands 0 = device ignore s write registers (wrr), program or erase commands this bit is not affected by wrr, only wren and wrdi commands affect this bit. 0 wip write in progress volatile, read only 0 1= device busy, a write re gisters (wrr), program, erase or other operation is in progress 0 = ready device is in standby mode and can accept commands table 63. configuration register (cr1) bits field name function type default state description 7 lc1 latency code non-volatile 0 selects number of init ial read latency cycles see latency code tables 6 lc0 0 5 tbprot configures start of block protection otp 0 1 = bp starts at bottom (low address) 0 = bp starts at top (high address) 4 rfu rfu otp 0 reserved for future use 3 bpnv configures bp2-0 in status register otp 0 1 = volatile 0 = non-volatile 2 tbparm configures parameter sectors location otp 0 1 = 4-kb physical sectors at top, (high address) 0 = 4-kb physical sectors at bottom (low address) rfu in uniform sector devices. 1 quad puts the device into quad i/o operation non-volatile 0 1 = quad 0 = dual or serial 0 freeze lock current state of bp2-0 bits in status register, tbprot and tbparm in configuration register, and otp regions volatile 0 1 = block protection and otp locked 0 = block protection and otp un-locked document number: 001-98282 rev. *i page 135 of 142 S25FL127S table 64. status register 2 (sr2) bits field name function type default state description 7 d8h_o block erase size otp 0 1 = 256 kb erase (uniform sectors). 0 = 64 kb erase (hybrid 4 kb / 64 kb sectors). 6 02h_o page buffer wrap otp 0 1 = wrap at 512b. 0 = wrap at 256b. 5 io3r_o io3 reset otp 0 1 = io3 alternate function is reset#. 0 = io3 alternate function is hold#. 4 rfu reserved 0 reserved for future use. 3 rfu reserved 0 reserved for future use. 2 rfu reserved 0 reserved for future use 1 es erase suspend volatile, read only 0 1 = in erase suspend mode. 0 = not in erase suspend mode. 0 ps program suspend volatile, read only 0 1 = in program suspend mode. 0 = not in program suspend mode. table 65. bank address register (bar) bits field name function type default state description 7 extadd extended address enable volatile 0b 1 = 4-byte (32-bits) addressing required from command. 0 = 3-byte (24-bits) addressing from command + bank address 6 to 2 rfu reserved volatile 00000b reserved for future use 1 ba25 bank address volatile 0 rfu for lower density devices 0 ba24 bank address volatile 0 rfu for lower density device table 66. asp register (aspr) bits field name function type default state description 15 to 9 rfu reserved otp 1 reserved for future use. 8 rfu reserved otp reserved for future use. 7 rfu reserved otp reserved for future use. 6 rfu reserved otp 1 reserved for future use. 5 rfu reserved otp reserved for future use. 4 rfu reserved otp reserved for future use. 3 rfu reserved otp reserved for future use. 2 pwdmlb password protection mode lock bit otp 1 0 = password protection mode permanently enabled. 1 = password protection mode not permanently enabled. 1 pstmlb persistent protection mode lock bit otp 1 0 = persistent protection mode permanently enabled. 1 = persistent protection mode not permanently enabled. 0 rfu reserved otp 1 reserved for future use. document number: 001-98282 rev. *i page 136 of 142 S25FL127S table 67. password register (pass) bits field name function type default state description 63 to 0 pwd hidden password otp ffffffff-ffffff ffh non-volatile otp storage of 64-bit password. the password is no longer readable after the password protection mode is selected by programming asp register bit 2 to 0. table 68. ppb lock register (ppbl) bits field name function type default state description 7 to 1 rfu reserved volatile 00h reserved for future use 0 ppblock protect ppb array volatile persistent protection mode = 1 password protection mode = 0 0 = ppb array protected until next power cycle or hardware reset 1 = ppb array may be programmed or erased table 69. ppb access register (ppbar) bits field name function type default state description 7 to 0 ppb read or program per sector ppb non-volatile ffh 00h = ppb for the sector addressed by the ppbrd or ppbp command is programmed to ?0?, protecting that sector from program or erase operations. ffh = ppb for the sector addressed by the ppbrd or ppbp command is erased to ?1 ?, not protec ting that sector from program or erase operations. table 70. dyb access register (dybar) bits field name function type default state description 7 to 0 dyb read or write per sector dyb volatile ffh 00h = dyb for the sector addressed by the dybrd or dybp command is cleared to ?0?, protec ting that sector from program or erase operations. ffh = dyb for the sector addr essed by the dybrd or dybp command is set to ?1?, not protecting that sector from program or erase operations. document number: 001-98282 rev. *i page 137 of 142 S25FL127S 12.5 initial delivery state the device is shipped from cypress with non-volatile bits set as follows: ? the entire memory array is erased: i.e. all bi ts are set to 1 (each byte contains ffh). ? the otp address space has the first 16 bytes programmed to a random number. all other bytes are erased to ffh. ? the sfdp address space contains the values as defined in the description of the sfdp address space. ? the id-cfi address space contains the values as def ined in the description of the id-cfi address space. ? the status register 1 contains 00h (all sr1 bits are cleared to 0?s). ? the configuration register 1 contains 00h. ? the autoboot register contains 00h. ? the password register contains ffffffff-ffffffffh ? all ppb bits are 1. document number: 001-98282 rev. *i page 138 of 142 S25FL127S ordering information 13. ordering information the ordering part number is formed by a valid combination of the following: valid combinations valid combinations list configurations planne d to be supported in volume for this device. consult your local sales office to co nfirm availability of specific valid combinations and to check on newly released combinations. table 71. S25FL127S valid combinations note: 1. example, S25FL127Sabmfi100 package marking would be fl127sif10 s25fl 127 s ab m f i 10 1 packing type 0 = tray 1 = tube 3 = 13? tape and reel model number (package details and reset#) 00 = soic16 footprint with reset# 10 = soic8/wson footprint c0 = 5 x 5 ball bga footprint with reset# d0 = 4 x 6 ball bga footprint with reset# = temperature range i = industrial (?40c to + 85c) v = industrial plus (?40c to + 105c) a = automotive, aec-q100 grade 3 (-40c to +85c) b = automotive, aec-q100 grade 2 (-40c to +105c) package materials f = lead (pb)-free h = low-halogen, lead (pb)-free package type m = 16-pin so / 8-pin so package n = 8-contact wson 6 x 5 mm package b = 24-ball bga 6 x 8 mm package, 1.00 mm pitch speed ab = 108 mhz device technology s = 0.065 m mirrorbit process technology density 127 = 128 mbit device family s25fl cypress memory 3.0 volt-only, serial peripheral interface (spi) flash memory valid combinations base ordering part number speed option package and temperature model number packing type package marking (1) S25FL127S ab mfi, mfv 00, 10 0, 1, 3 fl127 + s + (temp) + f + (model number) ab nfi, nfv 10 fl127 + s + (temp) + f + (model number) ab bhi, bhv c0, d0 0, 3 fl127 + s + (temp) + h + (model number) document number: 001-98282 rev. *i page 139 of 142 S25FL127S valid combinations ? au tomotive grade / aec-q100 the table below lists configurations that are automotive grade / aec-q100 qualified and are planned to be available in volume. the table will be updated as new combinations are released. consult your local sales representative to confirm availability of spec ific combinations and to check on newly released combinations. production part approval process (ppap) suppor t is only provided for aec-q100 grade products. products to be used in end-use applications that require iso/ts-16949 compliance must be aec-q100 grade products in combination with ppap. non?aec-q100 grade products are no t manufactured or documented in full compliance with iso/ts-16949 requirements. aec-q100 grade products are also offered without ppap suppor t for end-use applications that do not require iso/ts-16949 compliance. table 72. S25FL127S valid combinations ? automotive grade / aec-q100 valid combinations base ordering part number speed option package and temperature model number packing type package marking (1) S25FL127S ab mfa, mfb 00, 10 0, 1, 3 fl127 + s + (temp) + f + (model number) ab nfa, nfb 10 fl127 + s + (temp) + f + (model number) ab bha, bhb c0, d0 0, 3 fl127 + s + (temp) + h + (model number) document number: 001-98282 rev. *i page 140 of 142 S25FL127S 14. revision history document title: S25FL127S, 128-mbit (16 mbyte) 3.0 v spi flash memory document number: 001-98282 rev. ecn no. orig. of change submission date description of change ** ? bwha 12/11/2012 initial release *a ? bwha 04/25/2013 global: data sheet designation updated from advance information to preliminary performance summary: maximum read rates table: corrected dual and quad read ?clock rate? and ?mbytes/s? migration notes: fl generations comparison table: corrected dual read speed and quad read speed for fl127s dc characteristics: dc characteristics table: corrected icc1 test conditions for quad capacitance characteristics: capacitance table: updated note ac characteristics: ac characteristics table: corrected max value for fsck,c dual and quad command physical interface: 8-pin plastic small outline package (so) figure: corrected marking 8-contact uson 6x5 mm, top view figure: corrected marking 24-ball bga, 5 x 5 ball footprint (fab 024), top view figure: removed vio 24-ball bga, 4 x 6 ball footprint (fac024), top view: removed vio command set summary: S25FL127S command set (sorted by function) table: corrected maximum frequency for abrd, dor, 4dor, qor, 4qor, dior, 4dior, qior, 4qior embedded algorithm performance tables: added paragraph program and erase performance table: - added ?erase per sector? parameter - added note software interface reference: fl127s command set (sorted by instruction) table: corrected maximum frequency for dor, 4dor, qor, 4qor, dior, 4dior, qior, 4qior serial flash discoverable parameters (sfdp) address map: cfi alternate vendor-specific extended query para meter 90h ? latency code table: corrected description for 68h ordering information: valid combinations table: corrected package marking and note *b ? bwha 07/26/2013 features: added 16-pin soic package glossary: updated description of page signal descriptions: cha nged description of reset# hardware reset (reset#): changed r eset# description from ?may be left unconnected in the host system if not used? to ?should be left unconnected in the host system if not used? separate reset# input initiated ha rdware (warm) reset: changed reset# description from ?may be left unconnected? to ?should be left unconnected if not used? soic 16-lead package: added section ordering information: added 16-pin soic package *c ? bwha 09/11/2013 global: replaced uson with wson *d ? bwha 11/15/2013 global: data sheet designation updated from preliminary to full production physical interface: updated 8-pin plastic small outline package (so) figure command set summary: S25FL127S command set (sorted by function) table: added rsfdp command command summary: fl127s command set (sorted by instruction) table: added rsfdp command document number: 001-98282 rev. *i page 141 of 142 S25FL127S *e ? bwha 05/28/2015 jedec jesd216 serial flash discoverable parameters (sfdp) space: changed jesd216 to jesd216b serial flash discoverable parameters (sfdp) address map: updated section updated sfdp overview map table sfdp header field definitions: updated sfdp header table updated cfi alternate vendor-specific extended query parameter a5h, jedec sfdp table *f 4871631 bwha 08/24/2015 replaced ?automotive temperature range ? with ?industrial plus temperature range? in all instances across the document. updated to cypress template. *g 5348965 tocu 07/13/2016 updated serial flash discoverable para meters (sfdp) address map : updated device id and common flash interface (id-cfi) address map : updated field definitions : updated table 61 (updated entire table). updated to new template. *h 5670970 ecao 03/24/2017 updated cypress logo. updated sales page. updated features : added ecc information. added automotive temperature range support. updated section 1.3 glossary on page 7 : added ecc definition. updated section 4.2.1 temperature ranges on page 25 : added automotive temperature range support. updated table 19, register descriptions on page 50 : added ecc status register information. added section 7.6.6 ecc status register (eccsr) on page 56 updated section 8.1.2 programming otp memory space on page 59 : added ecc information. updated table 36, S25FL127S command set (sorted by function) on page 68 : added ecc read command information. updated section 9.3 register access commands on page 75 : added section 9.3.11 ecc status register read (eccrd 18h) on page 82 updated section 9.5 program flash array commands on page 93 : added section 9.5.1.1 automatic ecc on page 93 . updated table 44, fl127s command set (sor ted by instruction) on page 113 : updated figure 35, s0c008 ? 8-lead plastic small outline package (208-mil body width) on page 38 . updated figure 37, s03016 ? 16-lead wide plastic small outline package (300-mil body width) on page 40 . updated figure 41, fab024 ? 24-ball ball grid array (8 x 6 mm) package on page 44 . updated figure 43, fac024 ? 24-ball ball grid array (6 x 8 mm) package on page 46 . *i 5767544 ecao 06/08/2017 updated ordering information : no change in part numbers. updated table 71 and table 72 : fixed typo (replaced ?s25fl128s, s 25fl256s? with ?S25FL127S? in title). document title: S25FL127S, 128-mbit (16 mbyte) 3.0 v spi flash memory document number: 001-98282 rev. ecn no. orig. of change submission date description of change document number: 001-98282 rev. *i revised june 08, 2017 page 142 of 142 ? cypress semiconductor corporation, 2012-2017. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly desi gn, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear inst allations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage ("unintended uses"). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all uninte nded uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. S25FL127S sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot memory cypress.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power management ics cypress.com/pmic touch sensing cypress.com/touch usb controllers cypress.com/usb wireless connectivity cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support |
Price & Availability of S25FL127S
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |